The most complete ARM instruction set in history

Arithmetic and logical instructions

ADC : Addition with Carry

(Addition with Carry)

ADC{condition}{S} , , dest = op_1 + op_2 + carry

ADC will add two operands together and place the result in the destination register. It uses a carry flag so that additions larger than 32 bits can be made. The following example will add two 128-bit numbers.

128-bit result: Registers 0, 1, 2, and 3 First 128-bit number: Registers 4, 5, 6, and 7 Second 128-bit number: Registers 8, 9, 10, and 11

ADDS R0, R4, R8 ; add low-order word ADCS R1, R5, R9 ; add next word, with carry ADCS R2, R6, R10 ; add third word, with carry ADCS R3, R7, R11 ; add high-order word, with carry

If you are doing this addition, don't forget to set the S suffix to change the correct flag.

ADD : Addition

(Addition)

ADD{condition}{S} , , dest = op_1 + op_2

ADD will add its two operands together and place the result in the destination register. Operand 1 is a register, and operand 2 can be a register, a shifted register, or an immediate value:

ADD R0, R1, R2 ; R0 = R1 + R2 ADD R0, R1, #256 ; R0 = R1 + 256 ADD R0, R2, R3,LSL#1 ; R0 = R2 + (R3 << 1)

Addition can be performed on both signed and unsigned numbers.

AND : Logical AND

(logical AND)

AND{condition}{S} , , dest = op_1 AND op_2

AND performs a logical AND on its two operands, placing the result in the destination register; useful for masking bits you are working on. Operand 1 is a register, operand 2 can be a register, a shifted register, or an immediate value:

AND R0, R0, #3 ; R0 = Keep bits 0 and 1 of R0 and discard the rest.

Truth table for AND (if both are 1, the result is 1):

Op_1 Op_2 Result 0 0 0 0 1 0 1 0 0 1 1 1

BIC : Bit Clear

(Bit Clear)

BIC{condition}{S} , , dest = op_1 AND (!op_2)

BIC is a method of clearing bits in a word, the opposite of OR bit setting. Operand 2 is a 32-bit bit mask. If a bit in the mask is set, it is cleared. Unset mask bits indicate that the bit remains unchanged.

BIC R0, R0, #%1011 ; Clear bits 0, 1, and 3 in R0. Leave the rest unchanged.

BIC truth table:

Op_1 Op_2 Result 0 0 0 0 1 0 1 0 1 1 1 0

Note: The logical expression is Op_1 AND NOT Op_2

EOR : Logical exclusive OR

(logical Exclusive OR)

EOR{condition}{S} , , dest = op_1 EOR op_2

EOR performs a logical exclusive OR on the two operands, placing the result in the destination register; useful for inverting specific bits. Operand 1 is a register, operand 2 can be a register, a shifted register, or an immediate value:

EOR R0, R0, #3 ; Invert bits 0 and 1 in R0

EOR truth table (the result is 1 if the two are different):

Op_1 Op_2 Result 0 0 0 0 1 1 1 0 1 1 1 0

MOV : Transfer

(Move)

MOV{condition}{S} , dest = op_1

MOV loads a value from another register, a shifted register, or an immediate value into a destination register. You can specify the same register to achieve the effect of a NOP instruction, and you can also specifically shift a register:

MOV R0, R0 ; R0 = R0... NOP instruction MOV R0, R0, LSL#3 ; R0 = R0 * 8

If R15 is the destination register, the program counter or flags will be modified. This is used to return to the calling code by transferring the contents of the link register to R15:

MOV PC, R14 ; exit to caller MOVS PC, R14 ; exit to caller and restore flags (not compliant with 32-bit architecture)

MVN : Transmit the negated value

(MoveNegative)

MVN{condition}{S} , dest = !op_1

MVN loads a value from another register, a shifted register, or an immediate value into a destination register. The difference is that the bits are inverted before the transfer, so a negated value is transferred to a register. This is a logical NOT operation rather than an arithmetic operation, and the negated value plus 1 is its negation:

MVN R0, #4 ; R0 = -5 MVN R0, #0 ; R0 = -1

ORR : Logical OR

(logical OR)

ORR{condition}{S} , , dest = op_1 OR op_2

OR performs a logical OR on the two operands, placing the result in the destination register; useful for setting specific bits. Operand 1 is a register, operand 2 can be a register, a shifted register, or an immediate value:

ORR R0, R0, #3 ; Set bits 0 and 1 in R0

OR truth table (if 1 exists in either value, the result is 1):

Op_1 Op_2 Result 0 0 0 0 1 1 1 0 1 1 1 1

RS B : Reverse subtraction

(Reverse Subtraction)

RSB{condition}{S} , , dest = op_2 - op_1

SUB subtracts operand one from operand two, placing the result in the destination register. Operand 1 is a register, and operand 2 can be a register, a shifted register, or an immediate value:

RSB R0, R1, R2 ; R0 = R2 - R1 RSB R0, R1, #256 ; R0 = 256 - R1 RSB R0, R2, R3,LSL#1 ; R0 = (R3 << 1) - R2

Inverse subtraction can be performed on signed or unsigned numbers.

RSC : Reverse Subtraction with Borrow

(Reverse Subtraction with Carry)

RSC{condition}{S} , , dest = op_2 - op_1 - !carry

Same as SBC, but with the operands swapped.

SBC : Subtraction with Borrow

(Subtraction with Carry)

SBC{condition}{S} , , dest = op_1 - op_2 - !carry

SBC subtracts the two operands and places the result in the destination register. It uses the carry flag to indicate a borrow, so that it can do subtractions greater than 32 bits. SUB and SBC generate the carry flag differently than the normal way, clearing the carry flag if a borrow is required. Therefore, the instruction performs a negation on the carry flag - the bit is automatically inverted during the execution of the instruction.

SUB : Subtraction

(Subtraction)

SUB{condition}{S} , , dest = op_1 - op_2

SUB subtracts operand two from operand one and places the result in the destination register. Operand 1 is a register and operand 2 can be a register, a shifted register, or an immediate value:

SUB R0, R1, R2 ; R0 = R1 - R2 SUB R0, R1, #256 ; R0 = R1 - 256 SUB R0, R2, R3,LSL#1 ; R0 = R2 - (R3 << 1)

Subtraction can be performed on both signed and unsigned numbers.

Shift Instructions

The ARM processor has a barrel shifter that  can be used with data processing instructions (ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORR, RSB, SBC, SUB, TE Q, TST ) . You can also use the barrel shifter to affect the index value in LDR/STR operations.

Annotation: Shift operations are not used as separate instructions in the ARM instruction set. They are a field in the instruction format and are represented as options in the instruction in assembly language. If the second operand of a data processing instruction or the index in a single data transfer instruction is a register, various shift operations can be performed on it. If the second operand of a data processing instruction is an immediate value, it is represented in the instruction using an 8-bit immediate value and a 4-bit rotation. So for an immediate value greater than 255, the assembler tries to represent it by setting the rotation amount in the instruction, and generates an error if it cannot be represented. In logic class instructions, logical operation instructions determine whether the carry flag is affected by setting or clearing the S bit in the instruction, while the S bit of the comparison instruction is always set. The amount of shift can only be specified using an immediate value and not a register in a single data transfer instruction.

Here are six mnemonics for the different shift types:

LSL Logical Shift Left ASL Arithmetic Shift Left LSR Logical Shift Right ASR Arithmetic Shift Right ROR Rotate Right RRX Rotate Right with Extend

ASL and LSL are equivalent and can be used freely interchangeably.

You can specify the shift amount as an immediate value (from 0 to 31), or as a register containing a value between 0 and 31.

Logical or arithmetic left shift

(Logical or Arithmetic Shift Left)

Rx, LSL #n or Rx, ASL #n or Rx, LSL Rn or Rx, ASL Rn

Takes the contents of Rx and shifts them in the MSB direction by the amount specified by 'n' or in register Rn. The least significant bits are filled with zeros. The leftmost MSB is discarded except for the conceptual 33rd bit (which is the smallest bit shifted out). If the S bit is set in the logical instruction, this bit becomes the value of the carry flag on exit from the barrel shifter.

Consider the following:

MOV R1, #12 MOV R0, R1, LSL#2

On exit, R0 is 48. The sum formed by these instructions is R0 = #12, LSL#2 which is equivalent to B ASIC  's R0 = 12 << 2

Logical right shift

(Logical Shift Right)

Rx, LSR #n or Rx, LSR Rn

It is conceptually the opposite of left shift. It shifts all bits towards the less significant bits. If the S bit is set in the logic instruction, the last bit shifted out of the rightmost position is placed in the carry flag. It is the same as register = value >>> shift in BASIC.

Arithmetic right shift

(Arithmetic Shift Right)

Rx, ASR #n or Rx, ASR Rn

Similar to LSR, but uses the value of bit 31 of the register to be shifted (Rx) to fill the high bits, to preserve the sign in the two's complement representation. If the S bit is set in the logic instruction, the last bit shifted out of the rightmost position is placed in the carry flag. This is the same as register = value >> shift in BASIC.

Circular right shift

(Rotate Right)

Rx, ROR #n or Rx, ROR Rn

A circular right shift is similar to a logical right shift, but places the bits shifted out of the right side on the left side, and if the S bit is set in the logical instruction, places them in the carry flag, which is a 'loop' of the bits. A shift by 32 will result in an output that is exactly the same as the input, because all the bits have been shifted 32 places back to where they started!

Rotate right with extension

(Rotate Right with extend)

Rx, RRX

This is a ROR#0 operation, which shifts right one position - the difference is that it uses the processor's carry flag to provide a 33-bit amount to be shifted.

Multiplication Instructions

Instruction format:

These two instructions differ from ordinary arithmetic instructions in the restrictions on operands:

All operands and destination registers given must be simple registers.

You cannot use an immediate value or a shifted register for operand 2.

The destination register and operand 1 must be different registers.

Finally, you cannot specify R15 as the destination register.