Reset Status Register (RST_SR)
Address offset value: 0x00
Reset value: undefined
| Position 7:5 | Reserved bit, must remain 0 |
|---|---|
| Bit 4 | EMCF: EMC reset flag is set by hardware and can be cleared by software by writing "1" 0: No EMC reset occurs; 1: An EMC reset occurs (possible reset reasons: complementary registers or option bytes do not match). |
| Bit 3 | SWIMF: SWIM reset flag is set by hardware and can be cleared by software by writing "1". 0: No SWIM reset occurs; 1: A SWIM reset occurs. |
| Bit 2 | ILLOPF: The illegal operation code reset flag is set by hardware and can be cleared by software by writing "1". 0: No illegal operation code reset occurs; 1: An illegal operation code reset occurs. |
| Bit 1 | IWDGF: Independent watchdog reset flag is set by hardware and can be cleared by software by writing "1". 0: No IWDG reset occurs; 1: An IWDG reset occurs. |
| Bit 0 | WWDGF: Windowed watchdog reset flag is set by hardware and can be cleared by software by writing "1". 0: No WWDG reset occurs; 1: A WWDG reset occurs. |
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