ATmega168 Watchdog Timer

The watchdog timer is driven by an independent 128 kHz on-chip oscillator. The watchdog reset time interval can be adjusted by setting the prescaler of the watchdog timer, as shown in P44Table26. The watchdog reset instruction WDR is used to reset the watchdog timer. In addition, the watchdog timer is also reset when it is disabled or reset occurs. There are 10 options for the reset time. If the timer is not reset in time, once the time exceeds the reset period, the ATmega168 resets and executes the program pointed to by the reset vector. The specific watchdog reset timing is described in P44Table26.

The watchdog timer can also be used to generate an interrupt. This is very useful when using the watchdog to wake up the system from a power-down state.

To prevent the watchdog timer from being accidentally disabled or the reset time being changed, the fuse bit WDTON provides two different protection levels, as shown in Table 24. See P47 "Changing the timing sequence of the watchdog timer configuration".

Watchdog Timer Control Register - WDTCSR

· Bit 7 – WDIF: Watchdog Timeout Interrupt Flag
This bit is set when the watchdog timer times out and the timer is used as an interrupt. WDIF is cleared by hardware when the corresponding interrupt handler is executed. WDIF can also be cleared by writing "1" to the flag bit. When the I bit in the SREG register and WDIE are also set, the MCU executes a watchdog timeout interrupt.

Bit 6 – WDIE: Watchdog Timeout Interrupt Enable
When WDIE is set to "1", WDE is cleared, the I bit in the status register is set, and the watchdog timeout interrupt is enabled. When the watchdog timer times out, the corresponding interrupt routine is executed.

If WDE is set, WDIE is automatically cleared by hardware when a timeout occurs. This is very effective in ensuring the safety of watchdog reset when using interrupts. After the WDIE bit is cleared, the next timeout will cause a system reset. To avoid a watchdog reset, WDIE must be set after each interrupt.

Bit 4 – WDCE: Watchdog Modification Enable
WDCE must be set when WDE is cleared, otherwise the watchdog cannot be disabled. Once set, the hardware will clear it after the next 4 clock cycles. Please refer to the description of WDE to disable the watchdog. WDCE must also be set when modifying the prescaler, as shown in P47 "Time Sequence for Changing the Watchdog Timer Configuration".

· Bit 3 – WDE: Enable Watchdog
When WDE is “1”, the watchdog is enabled, otherwise the watchdog is disabled. WDE can only be cleared when WDCE is “1”. The following are the steps to disable the watchdog:
1. Write “1” to WDCE and WDE in the same instruction, even if WDE is already “1”.
2. Write “0” to WDE within the next 4 clock cycles. This will disable the watchdog.

When operating at safety level 2, the watchdog timer cannot be disabled even if the above algorithm is used. See “Time sequence for changing the watchdog timer configuration” on page 47.

When operating at safety level 1, WDE is replaced by the WDRF function of the MCUSR, see the description of WDRF in “MCU Status Register – MCUSR” on page 41. This means that when WDRF is set, WDE is also set. To clear WDE, WDRF must be cleared before disabling the watchdog using the above procedure. This feature ensures that there are multiple resets in the event of a fault and that it is safe to start after the fault is resolved.

Note: If the watchdog timer is not required in the application, the watchdog disabling procedure should be run during device initialization. If the watchdog is accidentally enabled, such as a program runaway or BOD, the device will reset and the WDRF flag will be set when the reset is exited. This will automatically activate the watchdog, causing a new watchdog reset. To avoid this situation, the application should clear the WDRF flag and the WDE control bit during the initialization process.

· Bits 5, 2..0 – WDP3..0: Watchdog Timer Prescaler 3, 2, 1, and 0
When the watchdog timer is enabled, WDP3..0 determines the watchdog timer prescaler as shown in Table 26.

The following examples implement the operation of turning off the WDT in assembly and C respectively. It is assumed that the interrupt is under user control (for example, the x global interrupt has been disabled), so the interrupt will not occur when executing the following program. 

Assembly code routine
WDT_off:
; Clear WDRF in MCUSR
ldi r16, ( 0<< WDRF ) 
out MCUSR, r16 ; Set WDCE and WDE 
ldi r16, (1<< WDCE )|( 1<< WDE ) ; Turn off WDT 
ldi r16, (0<< WDE ) 
out WDTCSR, r16
ret

C code routine
void WDT_off(void)
{
/* Clear WDRF in MCUSR */
MCUSR = 0x00
/* Set WDCE and WDE */
WDTCSR = (1<< WDCE) | (1<< WDE);
/* Turn off WDT */
WDTCSR = 0x00;
}