Common features of Timer_B and Timer_A
1 4 working modes
2 with optional, configurable counter input clock source
3. Multiple independent configurable capture/compare modules
4 There are multiple configurable output units with 8 output modes
5 DMA Enable
6 The interrupt function is powerful. The interrupt may come from the overflow of the counter, or from the capture event or comparison event occurring on each capture/compare module.
Differences between Timer_B and Timer_A
1 The count length of Timer_B is programmable to 8, 10, 12, and 16 bits, while the count length of Timer_A is fixed to 16 bits.
2 lThe function of the SCCI register bit in Timer_A is not implemented in Timer_B.
3The capture/compare register function of Timer_B in compare mode is different from that of Timer_A, and a compare latch is added
4 The Timer_B output in some chip models realizes high-impedance output
5 The principle of compare mode is slightly different: in Timer_A, the CCRx register stores the data to be compared with TAR; in Timer_B, the CCRx register stores the data to be compared, but it is not directly compared with the timer TBR. Instead, CCRx is sent to the corresponding latch, which is then compared with the timer TBR. The timing of transferring data from the capture/compare register to the compare latch is also programmable, either immediately after writing to the capture/compare register or triggered by a timer event.
6 Timer_B supports multiple, synchronous timing functions; multiple capture/compare functions; multiple waveform output functions (such as PWM signals). Moreover, through two-level buffering of comparison data, multiple PWM signal cycles can be updated synchronously.
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