STM8 PWM mode

STM8 PWM mode

The pulse width modulation (PWM) mode of the STM8 can generate a signal with a frequency determined by the TIM1_ARR register and a duty cycle determined by the TIM1_CCRi register.

Writing '110' (PWM mode 1) or '111' (PWM mode 2) to the OCiM bit in the TIM1_CCMRi register can independently set each OCi output channel to generate a PWM. The OCiPE bit in the TIM1_CCMRi register must be set to enable the corresponding preload register, and the ARPE bit in the TIM1_CR1 register can also be set to enable the automatic reload of the preload register (in the up-counting mode or the central symmetric mode).

Since the preload registers can be transferred to the shadow registers only when an update event occurs, all registers must be initialized by setting the UG bit in the TIM1_EGR register before the counter starts counting.

The polarity of OCi can be set by software in the CCiP bit in the TIM1_CCERi register, which can be set to high level active or low level active. The output enable of OCi is controlled by the combination of CCiE, MOE, OISi and OSSR bits and OSSI bits (in TIM1_CCERi and TIM1_BKR registers). See the description of the TIM1_CCERi register for details.

In PWM mode (mode 1 or mode 2), TIM1_CNT and TIM1_CCRi are always compared (depending on the counting direction of the counter) to determine whether TIM1_CCRi≤TIM1_CNT or TIM1_CNT≤TIM1_CCRi is met.

Depending on the state of the CMS bit field in the TIM1_CR1 register, the timer can generate edge-aligned PWM signals or center-aligned PWM signals.

PWM edge-aligned mode

• Up-count configuration
  When the DIR bit in the TIM1_CR1 register is low, up-counting is performed.
  The following is an example of PWM mode 1. When TIM1_CNTotherwise it is low. If the comparison value in TIM1_CCRi is greater than the auto-reload value (TIM1_ARR), OCiREF remains at '1'.
  If the comparison value is 0, OCiREF remains at '0'. The following figure is an example of edge-aligned PWM waveform when TIM1_ARR=8.
  

  
  (Figure 67: STM8 edge alignment, PWM mode 1 waveform (ARR=8))

• Down counting configuration
  Down counting is performed when the DIR bit of the TIM1_CR1 register is high.
  In PWM mode 1, the reference signal OCiREF is low when TIM1_CNT>TIM1_CCRi, otherwise it is high. If the comparison value in TIM1_CCRi is greater than the auto-reload value in TIM1_ARR, OCiREF remains at '1'. 0% PWM waveform cannot be generated in this mode.
  

PWM Center Aligned Mode

When the CMS bit in the TIM1_CR1 register is not '00', it is center-aligned mode (all other configurations have the same effect on the OCiREF/OCi signal).

Depending on the setting of the CMS bit, the compare flag can be set when the counter is counting up, counting down, or counting up and down. The count direction bit (DIR) in the TIM1_CR1 register is updated by hardware. Do not modify it by software. Refer to 17.3.6 Center-aligned mode.

Figure 68 shows some examples of center-aligned PWM waveforms.

• TIMx_ARR=8
  

• PWM Mode 1
  

• The flag bit is set in the following three cases (indicated by an arrow in the middle):
  ─ Only when the counter is counting down (CMS=01)
  ─ Only when the counter is counting up (CMS=10)
  ─ When the counter is counting up and down (CMS=11)
  

(Figure 68: STM8 center-aligned PWM waveform (APR=8))

Single pulse mode

The STM8 single pulse mode (OPM) is a special case of the above modes. This mode allows the counter to respond to a stimulus and generate a pulse with controllable pulse width after a programmable delay.

The counter can be started by the clock/trigger controller to generate waveforms in output compare mode or PWM mode. Setting the OPM bit in the TIM1_CR1 register selects the single pulse mode, where the counter automatically stops at the next update event UEV.

A pulse is generated only when the comparison value is different from the initial value of the counter. Before starting (when the timer is waiting for a trigger), it must be configured as follows:

• Upward counting mode: counter CNT

• Down counting mode: counter CNT>CCRi.

(Figure 48: STM8 single pulse mode example)

For example, you need to delay tDELAY after detecting a rising edge from the TI2 input pin to generate a positive pulse with a width of tPULSE on OC1:
Assume that IC2 is the trigger source of trigger channel 1:

• Set CC2S=01 in the TIM1_CCMR2 register to map IC2 to TI2.
  

• Set CC2P = 0 in the TIM1_CCER1 register to enable IC2 to detect the rising edge.
  

• Set TS=110 in the TIM1_SMCR register to make IC2 the trigger source (TRGI) of the clock/trigger controller.
  

• Set SMS = 110 (trigger mode) in the TIM1_SMCR register, and IC2 is used to start the counter.
  The OPM waveform is determined by the value written to the compare register (taking into account the clock frequency and the counter prescaler).
  

• tDELAY is defined by the value in the TIM1_CCR1 register.
  

• tPULSE is defined by the difference between the auto-reload value and the compare value (TIM1_ARR–TIM1_CCR1).
  

• Assume that a waveform from 0 to 1 is to be generated when a compare match occurs, and a waveform from 1 to 0 is to be generated when the counter reaches the preload value; first, set OCiM=111 in the TIM1_CCMR1 register to enter PWM mode 2; selectively set OC1PE=1 in the TIM1_CCMR1 register as needed, set ARPE in the TIM1_CR1 register to enable the preload register
  ; then fill in the compare value in the TIM1_CCR1 register, fill in the auto-load value in the TIM1_ARR register, set the UG bit to generate an update event, and then wait for an external trigger event on TI2.
  

In this example, the DIR and CMS bits in the TIM1_CR1 register should be set low.
Since only one pulse is required, set OPM=1 in the TIM1_CR1 register to stop counting at the next update event (when the counter rolls over from the auto-reload value to 0).

Special case: OCx fast enable

In single pulse mode, the edge detection on the TIi input pin sets the CEN bit to start the counter. Then the comparison operation between the counter and the compare value produces a single pulse output. However, these operations require a certain clock cycle, so it limits the minimum delay tDELAY that can be obtained.

If you want to output the waveform with minimum delay, you can set the OCiFE bit in the TIM1_CCMRi register; this forces OCiREF (and OCx) to respond directly to the stimulus and no longer rely on the comparison result, and the output waveform is the same as the waveform when the comparison matches.

OCiFE only works when the channel is configured in PWM1 and PWM2 mode.