LED bare metal program analysis three (header file Memcfg.ini)

In the header file of the myled bare metal program of mini2440, the header file Memcfg.ini defines the relevant configuration of the memory (the configuration of the memory-related register values, where the relevant configuration of the registers will eventually be called by init.s to initialize the CPU)

;************************************************

; NAME    : MEMCFG.A

; DESC   : Memory bank configuration file

; Revision: 02.28.2002 ver 0.0

; Revision: 03.11.2003 ver 0.0 Attatched for 2440

;************************************************

;Memory Area

;GCS6 32bit(64MB) SDRAM(0x3000_0000-0x33ff_ffff)

;Memory related configuration

;BWSCON

DW8 EQU (0x0) ; declare DW8 = 0x0;

DW16 EQU (0x1); declare DW16 = 0x1;

DW32 EQU (0x2); declare DW32 = 0x2;

WAIT EQU (0x1<<2)  ;声明WAIT=(0x1<<2);

UBLB EQU (0x1<<3);

ASSERT :DEF:BUSWIDTH ; Check if BUSWIDTH is defined. If not, terminate compilation and report an error.

;ASSERT :DEF:BUSWIDTH

;ASSERT is an assertion pseudo-instruction, the syntax is: ASSERT + logical expression 

;def is a logical pseudo-operator, the format is: :DEF:label, its function is to determine whether label has been defined 

; Addendum: [assert is used to evaluate the expression expression. If its value is false (that is, 0),

; then it prints an error message to stderr and then terminates the program by calling abort. ]

    [ BUSWIDTH=16

    ;16-bit bus width configuration

B1_BWSCON EQU (DW16)

B2_BWSCON EQU (DW16)

B3_BWSCON EQU (DW16)

B4_BWSCON EQU (DW16)

B5_BWSCON EQU (DW16)

B6_BWSCON EQU (DW16)

B7_BWSCON EQU (DW16)

    ;32-bit bus width configuration

    | ;BUSWIDTH=32 ; 2440 EV board.

B1_BWSCON EQU (DW32) ; Intel Strata(28F128), 32-bit, for nCS1 when NOR Flash booting.

B2_BWSCON EQU (DW16) ; PCMCIA(PD6710), 16-bit

B3_BWSCON EQU (DW16) ; Ethernet(CS8900), 16-bit

B4_BWSCON EQU (DW16) ; NOR flash(AM29LV800B), 16-bit,  for nCS4 when NAND booting.

B5_BWSCON EQU (DW16) ; A400/A410 Ext, 16-bit

B6_BWSCON EQU (DW32) ; SDRAM(K4S561632C) 32MBx2, 32-bit

B7_BWSCON EQU (DW32) ; N.C.

    ]

;BANK0CON [BANK0 register configuration]

B0_Tacs EQU 0x0 ;0clk [address setup time before nGCSn]

B0_Tcos EQU 0x0 ;0clk [chip select setup time before nOE]

B0_Tacc EQU 0x7 ;14clk [access cycle]

B0_Tcoh EQU 0x0 ;0clk [chip select hold time after nOE]

B0_Tah EQU 0x0 ;0clk [Address hold time after nGCSn]

B0_Tacp EQU 0x0 ; [Page mode access cycle in Page mode]

B0_PMC EQU 0x0 ;normal [Page mode configuration]

;BANK1CON [BANK1 register configuration]

B1_Tacs EQU 0x0 ;0clk

B1_Tcos EQU 0x0 ;0clk

B1_Tacc EQU 0x7 ;14clk

B1_Tcoh EQU 0x0 ;0clk

B1_Tah EQU 0x0 ;0clk

B1_Tacp EQU 0x0

B1_PMC EQU 0x0 ;normal

;Bank 2 parameter 【BANK2 register configuration】

B2_Tacs EQU 0x0 ;0clk

B2_Tcos EQU 0x0 ;0clk

B2_Tacc EQU 0x7 ;14clk

B2_Tcoh EQU 0x0 ;0clk

B2_Tah EQU 0x0 ;0clk

B2_Tacp EQU 0x0

B2_PMC EQU 0x0 ;normal

;Bank 3 parameter BANK3 register configuration

B3_Tacs EQU 0x0 ;0clk

B3_Tcos EQU 0x0 ;0clk

B3_Tacc EQU 0x7 ;14clk

B3_Tcoh EQU 0x0 ;0clk

B3_Tah EQU 0x0 ;0clk

B3_Tacp EQU 0x0

B3_PMC EQU 0x0 ;normal

;Bank 4 parameter

B4_Tacs EQU 0x0 ;0clk

B4_Tcos EQU 0x0 ;0clk

B4_Tacc EQU 0x7 ;14clk

B4_Tcoh EQU 0x0 ;0clk

B4_Tah EQU 0x0 ;0clk

B4_Tacp EQU 0x0

B4_PMC EQU 0x0 ;normal

;Bank 5 parameter

B5_Tacs EQU 0x0 ;0clk

B5_Tcos EQU 0x0 ;0clk

B5_Tacc EQU 0x7 ;14clk

B5_Tcoh EQU 0x0 ;0clk

B5_Tah EQU 0x0 ;0clk

B5_Tacp EQU 0x0

B5_PMC EQU 0x0 ;normal

;Bank 6 parameter

B6_MT EQU 0x3 ;SDRAM [determines the memory type of Bank6 and Bank7]

B6_Trcd EQU 0x2 ;4clk [RAS to CAS delay]

B6_SCAN EQU 0x1 ;9bit [column address number]

;Bank 7 parameter

B7_MT EQU 0x3 ;SDRAM

B7_Trcd EQU 0x2 ;4clk

B7_SCAN EQU 0x1 ;9bit

;REFRESH parameter [SDRAM refresh control register]

REFEN EQU 0x1 ;Refresh enable [SDRAM refresh enable]

TREFMD EQU 0x0 ;CBR(CAS before RAS)/Auto refresh [SDRAM refresh mode]

Trp EQU 0x2 ;4clk [SDRAM RAS precharge time]

Trc EQU 0x2 ;6clk [SDRAM half row cycle time]

Tchr EQU 0x2 ;3clk [bits 16 and 17 of the REFRESH register, not used by S3C2440A]

REFCNT EQU 1653 ;period=7.8us, HCLK=50.8Mhz, (2048+1-7.8*50.8) [refresh counter]

END