51 MCU resources - EEPROM (IIC bus)

Composition and working principle of I2C serial bus

The use of serial bus technology can greatly simplify the hardware design of the system, reduce the size of the system, and improve reliability. At the same time, the system can be easily modified and expanded.

I2C Serial Bus Overview

The I2C bus is a serial bus introduced by PHLIPS. It is a high-performance serial bus with bus arbitration and high- and low-speed device synchronization functions required by multi-host systems. 

The I2C bus has only two bidirectional signal lines, one is the data line SDA, and the other is the clock line SCL.

The I2C bus is connected to the positive power supply through a pull-up resistor. When the bus is idle, both lines are high. A low level output by any device connected to the bus will make the bus signal low, that is, the SDA and SCL of each device are in a line "AND" relationship.

Each device connected to the I2C bus has a unique address. Data transmission between the host and other devices can be done by the host sending data to other devices. In this case, the host is the transmitter. The device receiving data on the bus is the receiver.

In a multi-host system, there may be several hosts trying to start the bus to transfer data at the same time. To avoid confusion, the I2C bus must go through bus arbitration to decide which host controls the bus.

In the serial bus expansion of the 89C52 single-chip microcomputer application system, we often encounter a single-host situation with the 89C52 single-chip microcomputer as the host and other interface devices as slaves.

I2C bus data transmission

1. Data bit validity regulations:

When the I2C bus is transmitting data, the data on the data line must remain stable while the clock signal is at a high level (data is being transmitted at this time, so the data on the SDA line cannot change). The high or low level state of the data line is only allowed to change when the signal on the clock line is at a low level.

2. Start and stop signals

When the SCL line is at a high level, the change of the SDA line from a high level to a low level indicates a start signal;

When the SCL line is at a high level, the change of the SDA line from a low level to a high level indicates a termination signal.  

Both the start and stop signals are sent by the host. After the start signal is generated, the bus is in an occupied state; after the stop signal is generated, the bus is in an idle state.

3. Data transmission format

(1) Byte transmission and response

Each byte must be 8 bits long. When data is transmitted, the most significant bit (MSB) is transmitted first, and each transmitted byte must be followed by an acknowledge bit (i.e., a frame has a total of 9 bits).

When the slave does not respond to the host addressing signal for some reason (for example, the slave is performing real-time processing and cannot receive data on the bus), it must set the data line to a high level, and the host generates a termination signal to end the data transmission on the bus.

If the slave responds to the host but cannot receive more data after a period of data transmission, the slave can notify the host by "non-response" to the first data byte that cannot be received, and the host should send a termination signal to end the continued data transmission.

When the master receives data, it must send a signal to the slave to end the transmission after receiving the last data byte. This signal is implemented by a "non-acknowledge" to the slave. Then, the slave releases the SDA line to allow the master to generate a termination signal.

Regarding "Supplement to releasing the SDA line": Releasing the SDA line means setting SDA to 1. There is a pull-up resistor on both the data and clock lines of I2C, and the other end of the resistor is connected to a high level. When I2C is working, the level on SDA depends on the data on SDA. When I2C is not working, because the input end of the integrated circuit is in a high-impedance state, the voltage on SDA depends on the high level at the other end of the resistor. Therefore, after I2C releases the bus, SDA is equal to 1. This mainly depends on the structure of I2C and the specifications of the I2C bus.

(2) Data frame format

The data signals transmitted on the I2C bus are broad in nature, including both address signals and actual data signals.

After the start signal, a slave address (7 bits) must be transmitted. The 8th bit is the data transmission direction bit (R/T). "0" indicates that the host sends data (T), and "1" indicates that the host receives data (R). Each data transmission is always terminated by the termination signal generated by the host. However, if the host wants to continue to occupy the bus for new data transmission, it can not generate a termination signal and immediately send a start signal again to address another slave.

During a data transmission process on the bus, there can be the following combinations:

a. The host sends data to the slave, and the data transmission direction remains unchanged during the entire transmission process:

Note: The shaded area indicates that data is transmitted from the host to the slave, and the unshaded area indicates that data is transmitted from the slave to the host.

A means answer, A means no answer (high level). S means start signal, P means end signal

b. The host reads data from the slave immediately after the first byte

Read data from the slave immediately

c. During the transmission process, when the transmission direction needs to be changed, the start signal and the slave address are generated repeatedly, but the read/write direction bits are exactly inverted.

Note: When the two transmission directions are different, two start signals will be generated!

4. Bus addressing

The I2C bus protocol has clear provisions: use a 7-bit addressing byte (the addressing byte is the first byte after the start signal).

(1) Bit definition of addressing byte

D7 to D1 constitute the slave address. D0 is the data transfer direction bit. When it is "0", it means the host writes data to the slave, and when it is "1", it means the host reads data from the slave.

When the host sends an address, each slave on the bus compares the 7-bit address code with its own address. If they are the same, it believes that it is being addressed by the host and identifies itself as a transmitter or receiver based on the R/T bit.

The address of the slave consists of a fixed part and a programmable part. In a system, you may want to connect multiple identical slaves. The programmable part of the slave address determines the maximum number of devices of this type that can be connected to the bus. For example, if 4 of the 7 addressing bits of a slave are fixed bits and 3 are programmable bits, then only 8 identical devices can be addressed, that is, 8 identical devices can be connected to the I2C bus system.

Working principle of AT24CXX memory

Features

Compatible with 400KHz I2C bus

1.8 to 6.0 V operating voltage range

Low power CMOS technology

 Write protection function When WP is high, it enters the write protection state.

 Page Write Buffer

Self-timed erase and write cycles

1 million program/erase cycles

Data can be stored for 100 years

8-pin DIP SOIC or TSSOP package

Commercial and industrial temperature range

Overview

CAT24WC01/02/04/08/16 is a 1K/2K/4K/8K/16K bit serial CMOS, EEPROM contains 128/256/512/1024/2048 8-bit bytes CATALYST's advanced CMOS technology substantially reduces the power consumption of the device, CAT24WC01 has an 8-byte page write buffer CAT24WC02/04/08/16 has a 16-byte page write buffer, the device operates through the I2C bus interface has a dedicated write protection function

Bus Timing

Application of AT24C02 chip and I2C bus on development board

Writing process

The fixed part of the address of the AT24C series E2PROM chip is 1010. The A2, A1, and A0 pins are connected to high and low levels to obtain a certain 3-bit code. The 7-bit code formed is the address code of the device.

When the microcontroller performs a write operation, it first sends the 7-bit address code of the device and the write direction bit "0" (a total of 8 bits, i.e., one byte). After sending, the SDA line is released and the ninth clock signal is generated on the SCL line. After the selected memory device confirms that it is its own address, it generates a response signal on the SDA line as a response. After receiving the response, the microcontroller can transmit data.

When transmitting data, the microcontroller first sends a byte of the first address of the storage area to be written to the device. After receiving the response from the memory device, the microcontroller sends each data byte one by one, but waits for a response after sending each byte.

The on-chip address of the AT24C series device automatically increases by 1 after receiving each data byte address. Within the limit of the chip's "number of bytes loaded at one time" (different chips have different byte numbers), you only need to enter the first address. When the number of loaded bytes exceeds the chip's "number of bytes loaded at one time", the data address will be "rolled up" and the previous data will be overwritten.

When the data to be written is transmitted, the microcontroller should send a termination signal to end the write operation. The data format for writing n bytes is:

Reading process

The microcontroller first sends the 7-bit address code of the device and the write direction bit "0" ("dummy write"), then releases the SDA line and generates the ninth clock signal on the SCL line. After confirming that it is its own address, the selected memory device generates an acknowledgement signal on the SDA line as a response. 

 Then, send another byte of the first address of the storage area of ​​the device to be read. After receiving the response, the microcontroller will repeat the start signal and send the device address and read direction bit ("1"). After receiving the device response, the data byte can be read. Each time a byte is read, the microcontroller will reply with a response signal. When the last byte of data is read, the microcontroller should return to