Initialize the stack pointer SP (R13) in each mode of the ARM processor

Programming idea: The data transfer instruction MRS/MSR between the status register and the general register is used to implement the modification. The three steps of "read-modify-write back" should be used to implement the modification. Each time, only the corresponding domain needs to be modified. For example, this program only modifies the C control domain. At the same time, it should be noted that the system mode and user mode share SP, and only one of them needs to be initialized.

The program code is as follows:

(1) Programming in the GNU ARM development environment:

.equ _ISR_STARTADDRESS, 0xC7FF000 @Set the memory base address of the stack

.equ UserStack, _ISR_STARTADDRESS @User mode stack address 0x7FF000

.equ SVCStack, _ISR_STARTADDRESS+256 @ management mode stack address 0x7FF100

.equ UndefStack, _ISR_STARTADDRESS+256*2

.equ AbortStack, _ISR_STARTADDRESS+256*3

.equ IRQStack, _ISR_STARTADDRESS+256*4

.equ FIQ ​​Stack, _ISR_STARTADDRESS+256*5

.equ USERMODE, 0x10

.equ FIQMODE, 0x11

.equ IRQMODE, 0x12

.equ SVCMODE, 0x13

.equ ABORTMODE, 0x17

.equ UNDEFMODE, 0x1B

.equ SYSMODE, 0x1F

.equ MODEMASK, 0x1F

.global _start

.text

_start:

     MRS R0, CPSR @Read the current CPSR

     BIC R0, R0, #MODEMASK @ Clear mode bit

     #Set SP in user mode

     ORR R1, R0, #SYSMODE

     MSR CPSR_c, R1

     LDR SP, =UserStack

     #Set SP in undefined mode

     ORR R1, R0, #UNDEFMODE

     MSR CPSR_c, R1

     LDR SP, =UndefStack

     #Set the SP in termination mode

     ORR R1, R0, #ABORTMODE

     MSR CPSR_c, R1

     LDR SP, =AbortStack

     #Set the SP in management mode

     ORR R1, R0, #SVCMODE

     MSR CPSR_c, R1

     LDR SP, =SVCStack

     #Set SP in IRQ mode

     ORR R1, R0, #IRQMODE

     MSR CPSR_c, R1

     LDR SP, =IRQStack

     #Set SP in FIQ mode

     ORR R1, R0, #FIQMODE

     MSR CPSR_c, R1

     LDR SP, =FIQStack

Stop:

     B Stop

.end

(2) The program execution results are as follows:

     SP_usr=0xC7FF000

     SP_svc=0xC7FF100

     SP_und=0xC7FF200

     SP_abt=0xC7FF300

     SP_irq=0xC7FF400

     SP_fiq=0xC7FF500