ARMv7 architecture study notes (I)

This round of learning process mainly focuses on the learning of ARM NEON technology, mainly including the learning of instructions and the summary of programming skills.

ARM NEON technology is an optional component of the ARMv7 architecture. NEON is a 64/128-bit hybrid SIMD technology for advanced media and signal processing applications and embedded processors. It is implemented as part of the ARM core, but has its own execution pipeline and register set, which is different from the ARM core register set.

NEON supports integer, fixed-point, and single-precision floating-point SIMD operations. These instructions are available in both ARM and Thumb-2.

NEON extension register set:

--- 16-128bit four-word register Q0~Q15

--- 32-64bit double word register D0~D31

Many NEON data processing instructions are available in normal, long, wide, narrow, and saturating variants. NEON instructions can process:

* A doubleword vector consisting of:

---8 8-bit elements

---4 16-bit elements

---2 32-bit elements

---1 64-bit element

* A quadword vector consisting of

---16 8-bit elements

---8 16-bit elements

--- 4 32-bit elements

--- 2 64-bit elements

Normal instructions

Normal instructions can operate on any of the above vector types and produce a result vector of the same size and usually the same type as the operand vector. You can specify that the operands and results of normal instructions must all be quadwords by appending Q to the instruction mnemonic. When this is specified, the assembler generates an error if either the operand or the result is not a quadword.

Long instructions

Long instructions operate on doubleword vector operands and produce a quadword vector result. The elements produced are usually twice the width of the operand elements and are of the same type. Long instructions are specified by appending L to the instruction mnemonic.

Wide Instructions

Wide instructions operate on a doubleword vector operand and a quadword vector operand. Such instructions produce a quadword vector result. The elements produced and the elements of the first operand are twice the width of the elements of the second operand. Wide instructions are specified by appending W to the instruction mnemonic.

Narrow instructions

Narrow instructions operate on quadword vector operands and produce doubleword vector results. The elements produced are usually half the width of the operand elements.
Narrow instructions are specified by appending N to the instruction mnemonic.

Saturation Instructions

Saturating instructions are specified by using a Q prefix between the V and the instruction mnemonic.