Introduction to PIC32 SPI (Master/Slave Mode)

SPI serial synchronous interface (with clock pulse)

The Serial Peripheral Interface (SPI) module is a synchronous serial interface used to communicate with external peripherals and other microcontroller devices. These peripherals can be serial EEPROMs, shift registers, display drivers, and analog-to-digital converters.

(ADC) or audio codec.

The SPIx serial interface consists of the following four pins: (The four pins can be determined by the pin mapping)

SDIx: Serial data input

SDOx: Serial Data Output

SCKx: shift clock input or output

SSx: Low dynamic power slave select or frame synchronization I/O pulse

The working principle of the SPI module in master mode is as follows:

To summarize in one sentence: Data is written into SPIxbuf by the user and then loaded into the SPIXTXB transmit buffer and moved into the shift register SPIxSR. Only when there is data to be sent does the baud generator generate a clock pulse corresponding to the data bit pattern. One pulse and one data bit are synchronously sent from the shift register SPIxSR to the data output pin SDOX.

1. Once the module is set up for Master mode operation and enabled, the data to be transmitted is written to the SPIxBUF register.

The SPITBE bit (SPIxSTAT<3>) is cleared.

2. The contents of SPIxTXB are shifted into the shift register, SPIxSR (see Figure 23-8), and the module clears the SPITBE bit.

3. A set of 8/16/32 clock pulses shifts 8/16/32 bits of transmit data out of the SPIxSR to the SDOx pin.

Data from the SDIx pin is shifted into the SPIxSR.

4. When the transfer is complete, the following events occur:

a) Set the interrupt flag bit SPIxRXIF to 1. Enable the SPI interrupt by setting the interrupt enable bit SPIxRXIE to 1.

The SPIxRXIF flag is not automatically cleared by hardware.

b) Additionally, when the ongoing transmit and receive operations are completed, the contents of SPIxSR are moved into SPIxRXB.

c) The module sets the SPIRBF bit (SPIxSTAT<0>) to indicate that the receive buffer is full.

SPIxBUF, the hardware will clear the SPIRBF bit. In Enhanced Buffer mode, the SPIRBE bit (SPIxSTAT<5>)

Will be set when the SPIxRXB FIFO buffer is completely empty and cleared if not completely empty.

5. When the SPI module needs to transfer data from SPIxSR to SPIxRXB, if the SPIRBF bit is set (receive
buffer is full), the module sets the SPIROV bit (SPIxSTAT<6>), indicating an overflow condition.

6. User software can write data to be transmitted to
the SPIxBUF at any time as long as the SPITBE bit (SPIxSTAT<3>) is set. The write operation can occur simultaneously with the SPIxSR shifting out previously written data, thus allowing continuous transmission.
In Enhanced Buffer mode, the SPITBF bit (SPIxSTAT<1>) is set when the SPIxTXB FIFO buffer is full
and cleared when it is not full.
SPITBE: SPI Transmit Buffer Empty Status bit(1) (empty)
1 = Transmit buffer SPIxTXB is empty
0 = Transmit buffer SPIxTXB is not empty
This bit is automatically set by hardware when the SPI transfers data from SPIxTXB to SPIxSR.
This bit is automatically cleared by hardware when SPIxBUF is written to load SPIxTXB.
SPITBF: SPI Transmit Buffer Full Status bit(1) (full)
1 = Transmit has not started yet, SPIxTXB is full
0 = Transmit buffer is not full
Standard Buffer mode:
Automatically set by hardware when the core writes to the SPIxBUF location, loading SPIxTXB.
Automatically cleared by hardware when the SPI module transfers data from SPIxTXB to SPIxSR.
Enhanced Buffer mode:
Set when there is no space available in the FIFO.

CKE: SPI clock edge selection bit (edge)
1 = Serial output data changes when the clock changes from the working state to the idle state (see CKP bit)
0 = Serial output data changes when the clock changes from the idle state to the working state (see CKP bit)
CKP: Clock polarity selection bit (polarity)
1 = The clock signal is high in the idle state; low in the working state
0 = The clock signal is low in the idle state; high in the working state

When and only when the shift register SPIXSR has data to be sent, a clock pulse is generated, the clock idle polarity is determined by CKP, and
the clock edge for data transmission is determined by CKE.

For example, in 8-bit data mode, 8 clock pulses are generated, and each clock pulse sends one bit of data to achieve synchronous data transmission. After a piece of data is transmitted, an interrupt SPIxRXIF is generated (this event will occur when new data is collected in the SPIxBUF receive buffer.)

1 Master Mode Operation
To set the SPI module to work in master mode, follow these steps:
1. Disable the SPI interrupt in the corresponding IECx register. mSPI1TXIntEnable(0); //Transmit complete interrupt

2. Stop and reset the SPI module by clearing the ON bit. SPI1CON=0; //Clear bit 15

3. Clear the receiving buffer. rData=SPI1BUF; // Clear after reading the SPI buffer data

4. Clear the ENHBUF bit (SPIxCON<16>) if using Standard Buffer mode or set it if using Enhanced Buffer mode. SPI1CONCLR = 0X10000;

5. If you do not want to use the SPI interrupt, skip this step and proceed to Step 5. Otherwise, perform the following additional steps:
a) Clear the SPIx interrupt flag/event in the corresponding IFSx register.
b) Write the SPIx interrupt priority and subpriority bits in the corresponding IPCx register.
c) Set the SPIx interrupt enable bit in the corresponding IECx register
. 6. Write the Baud Rate Generator register, SPIxBRG.
7. Clear the SPIROV bit (SPIxSTAT<6>).
8. Write the desired settings to the SPIxCON register with MSTEN (SPIxCON<5>) = 1.
9. Enable SPI operation by setting the ON bit (SPIxCON<15>).
10. Write the data to be transmitted to the SPIxBUF register. Transmission (and reception) begins as soon as data is written to the SPIxBUF register.

1. Configure pin mapping (determined by the actual pin situation)             
PPSOutput(2, RPB8, SDO2); or RPB8Rbits.RPB8R=0B0100;  
PPSInput(2,SDI2,RPB13); or SDI2bits.SDI2=0B0011;

2. Initialize SPI
using library function SpiChnOpen(SpiChannel chn, SpiOpenFlags oFlags, unsigned int srcClkDiv);
SPIChannel channel 1, 2 is SPI1/SPI2,
SpiOpenFlags open configuration (see library function SPI.h) Appendix 1
Example SpiOpenFlags oFlags = SPI_OPEN_MSTEN | SPI_OPEN_CKP_HIGH | SPI_OPEN_MODE8 | SPI_OPEN_ON;
Master mode, high voltage when clock is idle, 8-bit data mode, open SPI. Other defaults 0
srcClkDi Baud frequency division of peripheral clock, thus determining the speed of sending data clock pulse
FSCK=FPB/(2*(SPIxBRG+1)) BRG is a 9-bit register (0-511) FSCK(FPB/2-FPB/1024)

2 Slave Mode Operation
To set up the SPI module for Slave mode of operation, follow these steps:
1. If using interrupts, disable the SPI interrupts in the corresponding IECx register.
2. Stop and reset the SPI module by clearing the ON bit.
3. Clear the receive buffer.
4. Clear the ENHBUF bit (SPIxCON<16>) if using Standard Buffer mode or set it if using Enhanced Buffer
mode
. 5. If interrupts are to be used, the following additional steps are required:
a) Clear the SPIx interrupt flag/event in the corresponding IFSx register.
b) Write the SPIx interrupt priority and subpriority bits in the corresponding IPCx register.
c) Set the SPIx interrupt enable bit in the corresponding IECx register .
6. Clear the SPIROV bit (SPIxSTAT<6>).
7. Write the desired settings to the SPIxCON register with MSTEN (SPIxCON<5>) = 0.
8. Enable SPI operation by setting the ON bit (SPIxCON<15>).
9. Transmission (and reception) begins as soon as the master provides the serial clock.
In Slave mode, data transmission and reception begins with an external clock pulse on the SCKx pin. The CKP bit (SPIxCON<6>)
and CKE bit (SPIxCON<8>) determine on which edge of the clock the data is transmitted.

1. Configure pin mapping (determined by the actual pin situation)             
PPSOutput(2, RPB8, SDO2); or RPB8Rbits.RPB8R=0B0100;  
PPSInput(2,SDI2,RPB13); or SDI2bits.SDI2=0B0011;
2. Initialize SPI
using library function SpiChnOpen(SpiChannel chn, SpiOpenFlags oFlags, unsigned int srcClkDiv);
SPIChannel channel 1 and 2, namely SPI1/SPI2,
SpiOpenFlags enabled configuration (see library function SPI.h)
For example,
SpiOpenFlags oFlags =
SPI_OPEN_SLVEN | SPI_OPEN_SSEN | SPI_OPEN_CKP_HIGH | SPI_OPEN_MODE8 | SPI_OPEN_ON;
Slave mode, slave select enable SSx The pin is used for slave mode, high voltage when the clock is idle, 8-bit data mode, and SPI is turned on. Other defaults are 0
srcClkDi The baud frequency division of the peripheral clock, thereby determining the speed of the data clock pulse to be sent
FSCK=FPB/(2*(SPIxBRG+1)) BRG is a 9-bit register (0-511) FSCK(FPB/2—FPB/1024)

The following additional features are provided in Slave mode:
Slave Select SynchronizationThe
SSx pin allows Synchronous Slave mode. If the SSEN bit (SPIxCON<7>) is set,
transmission and reception in Slave mode are enabled only when the SSx pin is driven low. For the SSx pin to function as an input, the port output or other peripheral outputs cannot be driven. If the SSEN bit is set and the SSx pin is driven high, the SDOx pin will no longer be
driven and will become tri-stated, even if the module is in the process of transmitting. The next time the SSx pin is driven low, an aborted transmission will be retried with the data held in the SPIxTXB register. If the SSEN bit is not set, the SSx pin has no effect on the operation of the module in Slave mode.

Operation of the SPITBE Status FlagThe
function of the SPITBE bit (SPIxSTAT<3>) is different in Slave mode of operation. The following describes
the SPITBE function for various Slave mode settings:

- SPITBE
is cleared . It is set when the module transfers data from SPIxTXB to SPIxSR. This
is similar to the functionality of the SPITBE bit in Master mode.

- If SSEN is set, SPITBE is cleared when the user code loads data into SPIxBUF. However, it
is set only when the SPIx module completes transmitting data. When the SSx pin goes high, the transmission is aborted but
may be retried later. Therefore, each data word is held in SPIxTXB until all bits are
transmitted to the receiver.