Design of digital FM radio using single chip microcomputer + CXA1019S + phase-locked loop BU2614

                          Figure-8

In the circuit, as shown in the schematic diagram of the FM signal generator, inductor L1 and capacitor C form a parallel resonant circuit. DC blocking capacitors C5 and C8 are added in the figure. In addition, C5 and C8 also act as coupling capacitors for high-frequency oscillation signals. C5 and C8 are 1000PF, which is much larger than CD. That is to say, no matter how low the reverse bias voltage of the varactor diode is, C5, C8>>CD will always hold true.

The variable capacitance diode adopts the partial access method, which has good linearity. In practical applications, the linear range of voltage-controlled oscillation characteristics is limited. Beyond this range, the control sensitivity will decrease. In practical applications, we often use linearity. In this circuit, Uc is taken from 2.6v to 9.8v for practical use.

D. Frequency divider (N)

This design uses the shift register inside the integrated chip BU2614 to form a frequency divider. Its frequency division coefficient N is determined by the microcontroller program and finally realized through the communication between the microcontroller and BU2614. BU2614 has three serial communication ports (CE, CK, DATA). The communication timing and data transmission format of these three ports and the microcontroller are shown in Figure-9:

                                  Figure-9

Among them, R0, R1, and R2 are standard frequency bits. This design selects 000, which is 25KHZ. S is the FMIN and AMIN selection switch. 0 indicates FM input and 1 indicates AM input. This design is FM, so S is 0. The remaining bits are irrelevant when BU2614 is used as a frequency synthesizer, and are all selected as 0. For the first sixteen data bits (D0~D15), the transmission format is:

Frequency division number N: from D0 to D15 (when S=1, use D4 to D15)

This design chooses the format of S=0, PS=0.

    In this design, the core component of the phase-locked loop circuit is the BU2614 phase-locked frequency synthesis chip. It forms a complete phase-locked frequency synthesis circuit with the peripheral tuning circuit and the local oscillator circuit. It adjusts the local oscillator frequency through the frequency division ratio preset by the single-chip microcomputer. If the angular frequency of the voltage-controlled oscillator changes, the voltage input to the phase detector and the output voltage will definitely produce corresponding phase changes. The phase detector will output an error voltage proportional to the phase error, and the slowly changing DC voltage will be taken out through the loop filter to control the frequency of the voltage-controlled oscillator output signal, so that the phase difference between the input and output signals of the phase-locked loop is reduced until the frequency of the voltage-controlled oscillator output signal is equal to the input signal frequency, the phase difference is equal to a constant, and the phase-locked loop enters a locked state. Thus, the radio reception tuning and frequency stabilization function is completed.

3.3 Display Circuit

This part of the design uses the MAX7219 serial display control chip to replace the conventional non-gate driver chip, such as 74LS00, which greatly simplifies the display circuit and achieves the requirements of using the least devices, the smallest power consumption, and improving the stability of the circuit in the shortest time. MAX7219 is a serial interface 8-bit digital static display chip with complete functions and low system resource consumption.

The three ports P3.3, P3.4 and P3.5 of AT89C52 are used. The circuit is shown in Figure 10.

3.4 Keyboard Circuit                                    

For the design of function keys, we adopted the query method, that is, the P1.2~P1.7 ports of the 89C52 microcontroller are used as function key interfaces, the P0 and P2 ports of the microcontroller are used as I/O ports, and P0.6, P0.7 and P2.0~P2.4 are used to form 10 coded dynamic scanning matrix keys. These 10 keys are used as both numeric keys 0~9 and as 10 station numbers for storing radio stations. In addition, six ports P0.0~P0.5 are connected to six light-emitting diodes as working status indicators for the six function keys. The specific circuit is shown in Figure-11.

                       Figure-11

3.5 Power-off data storage circuit

  Since the serial EEPROM 93C46 has an online erase function, this design uses it to store radio data so that all stored radios can be called out when the machine is restarted. 93C46 is a 64*16 (1024) bit serial access electrically erasable programmable read-only memory with online data rewrite and automatic erase functions; data is not lost regardless of power on or off; its connection with the microcontroller is shown in Figure 10, and communication is mainly completed through ports CS, SK, DI and DE. Among them, CS is the chip select line, and the input high level has Figure-12

When CS=1, the chip can be read and written. The falling edge of the signal added to the CS terminal starts the internal timing circuit to start the erase and write operation. SK is the external trigger clock signal input for serial data input or output, and the input clock frequency is 0~250KHZ. DI is the serial data input terminal. DE is the serial data output terminal. During read and write operations, OUT can be used as an erase and write status indication equivalent to the READY/BUSY signal. In other states, OUT is in a high impedance state. When BPE is connected to a high level, the chip erase and write instructions are valid.

3.6 Program running monitoring circuit

  The program running monitoring system is also called a watchdog circuit (WATCHDOG). Its main function is to prevent the program from jumping into a temporary infinite loop. The features of WATCHDOG are:

• It can work independently and basically does not rely on the CPU.

• The CPU interacts with the system once at a fixed time interval to indicate that the system is "currently normal."

• When the CPU falls into an infinite loop, it can detect it in time and reset the system.
  

    This design uses a counting type WATCHDOG circuit, and its circuit diagram is shown in Figure-13. The hardware part of the WATCHDOG is a monostable component independent of the CPU, and is composed of a counter with its own pulse source. Connect 555 to a multivibrator with a period of t0, and connect CD4017 to a decimal counter. When the tenth pulse is the QA end, it becomes a high level. The microcontroller uses an output port (P3.6) to output a clear pulse. As long as each clear pulse is Figure-13

If the time interval between the pulses is shorter than ten pulse cycles, the counter will never reach ten, and the QA terminal will remain at a low level. When the CPU is disturbed and falls into an infinite loop, it cannot send a reset pulse. The counter quickly counts to ten, and QA immediately becomes a high level, outputting a positive pulse to reset the CPU. Here, the system has three reset signals: power-on reset (C1, R1), manual reset (K, R2, R1) and WATCHDOG reset (P3.6), which are added to the RESET terminal after passing through the integrated gate.

3.7 Power supply

The DC-DC dedicated chip LT1930 from Linear Corporation was selected, and the typical circuit was improved to enable it to output +12V. The circuit is shown in Figure 14.

                                        Figure-14

3.8 MCU Part

The single-chip microcomputer system is the core control part of the radio. Its task is to read the control instructions from the keyboard, output the corresponding serial data to control the frequency division ratio of the frequency synthesizer, and then adjust and control the frequency of the tuning circuit and the local oscillator circuit through the phase-locked loop, so as to realize program-controlled search, radio station storage, call out the radio station number, display the carrier frequency and display the status information of the radio. Its block diagram is shown in Figure-15:

For the storage of radio, static memory RAM is generally used to store information, but RAM will lose data after power failure. For this reason, we use 93C46 chip with online reading and writing and power failure saving functions to complete the storage function. Since the receiving frequency of this radio is 88MHz ~ 108MHz Figure-15

With a step size of 25KHz, a total of 800 frequency points need to be measured. Considering the actual situation in this area, the number of storage units in this system is set to 10.

Chapter 4 Software System

4.1 Main Program

The function keys of this design adopt the query mode, and the number keys adopt the dynamic scanning mode. After the radio is turned on, first tune in the radio station when it was turned off last time, and restore the radio frequency data stored for each station number before the last shutdown. Then start to dynamically scan each number key to determine whether to directly call the stored radio station. If a number key is pressed, the radio station already under the key is called and the frequency of the radio station is displayed. If no number key is pressed, it will go into the judgment function key. When a function key is pressed, the corresponding function is executed. If no function key is pressed, the current radio station data is stored and then returned to continue the cyclic scan. The main program flow chart is shown in Figure-16

4.2 Function Key Query Program

According to the design requirements, six function keys are arranged: full-frequency search key, continue search key, specified frequency range search key, up step key, down step key and storage key. When the program executes to the function key query, if a key is pressed, it will transfer to each function key. After the full-frequency search is executed, the radio will search upward from 88MHZ in steps of 25KHZ. If there is no locked station signal, the radio will search until 108MHZ before jumping out. When there is a locked station signal, it will stay on the station. The continue search program starts from the current frequency and searches upward. If there is no locked station signal, the radio will search until 108MHZ before jumping out. When there is a locked station signal, it will stay on the station. The specified frequency range search program is that when this key is pressed, the digital tube automatically displays "LP" to prompt the minimum value of the frequency range to be entered. After entering the value, press the OK key, and it will display "HP" to prompt the maximum value of the frequency range to be entered. After entering the value, press the OK key, and it will automatically start from the minimum frequency point and search in steps of 25KHz. When the radio station is found, it will automatically enter the radio state. If the input frequency value is not within the frequency band 88MHz ~ 108MHz covered by this machine or the maximum value entered is less than the minimum value entered, "OP" will be displayed to prompt the input error. The upward step and downward step programs are manual searches with 25KHZ as steps. The station storage program is to call the dynamic scan key program after pressing this key, and then press the number key to get the key number and store the corresponding frequency in the corresponding storage unit. See Figure 1 for the program flow chart of this part.