ARM9 SWI software interrupt

1. SWI software interrupt principle.

In privileged mode, processor mode switching can be switched through software control, that is, modifying the mode bit of CPSR. However, in user mode, there is no authority to implement mode switching by modifying CPSR, unless switching is performed through external interrupts or exception handling. In order to facilitate flexible mode switching in user mode, the ARM instruction set provides instructions that generate exceptions, namely the software interrupt instruction SWI. In other words, the user program can switch to privileged mode by writing the SWI instruction. When the CPU executes the SWI instruction, it will switch from user mode to management mode and execute software interrupt processing. The SWI instruction can also be used in other modes, and the processor also switches to management mode. 

Instruction format:

SWI{cond} immed_24 

Among them: immed_24 is a 24-bit immediate value, and its value is an integer between 0 and 16777215. It is used as a connection code between the user program and the soft interrupt processing program. The soft interrupt immediate value is used to distinguish different user operations. 

Instruction encoding format: 

Command example: 

SWI 1; Generate soft interrupt No. 1

Instruction Description: 

Calling the SWI soft interrupt instruction in user mode can cause the processor to jump to the address corresponding to the SWI interrupt vector table, and then jump into the soft interrupt handler.

In the soft interrupt handler, different operations can be performed according to the soft interrupt number. The method for determining the soft interrupt number is as follows: 

LDR R4, [LR, #-4]; LR is the hardware automatically saves the next instruction address of SWI xxx instruction

; LR – 4 is the SWI instruction address

BIC R4, R4, #0xFF000000; Clear the upper 8 bits of the SWI instruction and keep only the lower 24 bits.

; That is, get the SWI instruction code, then R4 is SWI

;Soft interrupt number after the instruction; 

2. Code

AREA Stack1,DATA,READWRITE

stack1 DCD 10*512

PRESERVE8

AREA TEST,CODE,READONLY

CODE32

ENTRY

b reset

b _undefined_instruction

b _software_interrupt

b _prefetch_abort

b _data_abort

b _not_used

b_irq

b _fiq

_undefined_instruction

nop

_prefetch_abort

nop

_data_abort

nop

_not_used

nop

_irq

nop

_fiq

nop

reset

mrs r0,cpsr

bic r0,r0,#0x1f

orr r0,r0,#0xd3

msr cpsr_c,r0 ;Enable svc mode of cpu

init_stack

ldr r0,=stack1 ;get stack top pointer*/

;svc mode stack

mov sp,r0

sub r0,#128*4 ;/*512 byte for irq mode of stack*/

;/****irq mode stack**/

msr cpsr_c,#0xd2

mov sp,r0

sub r0,#128*4 ;/*512 byte for irq mode of stack*/

;/***fiq mode stack***/

msr cpsr_c,#0xd1

mov sp,r0

sub r0,#0

;/***abort mode stack***/

msr cpsr_c,#0xd7

mov sp,r0

sub r0,#0

;/***undefine mode stack***/

msr cpsr_c,#0xdb

mov sp,r0

sub r0,#0

;/*** sys mode and usr mode stack ***/

msr cpsr_c,#0x10

mov sp,r0 ;/*1024 byte for user mode of stack*/

swi 1

swi 2

LOOP

B LOOP

_software_interrupt

STMFD SP!, {R0-R4, LR} ; Save program execution scene

LDR R4, [LR, #-4]; LR - 4 is the address of instruction "swi xxx", the lower 24 bits are the software interrupt number

BIC R4, R4, #0xFF000000 ; Get ARM instruction 24-bit immediate value

CMP R4, #1

ADDEQ R5,R5,#1 ; Check the 24-bit immediate value. If it is 1, execute R5+1 operation.

LDREQ PC, =swi_return; Soft interrupt processing returns CMP R4, #2; Check the 24-bit immediate value, if it is 2, execute R6+1 operation

ADDEQ R6,R6,#1

LDREQ PC, =swi_return; soft interrupt processing return address

swi_return

LDMFD SP!, {R0-R4, PC}^; Interrupt return, ^ means copy the value of spsr to cpsr

END

PS:

1. bic

The format of the BIC instruction is:

BIC{condition}{S} destination register, operand 1, operand 2

The BIC instruction is used to clear certain bits of operand 1 and place the result in the destination register. Operand 1 should be a register.

Operand 2 can be a register, a shifted register, or an immediate value. Operand 2 is a 32-bit mask.

If a bit in the mask is set to 1, the bit is cleared. Unset mask bits remain unchanged.

bic r0,r0,#0x1f

0x1f=11111b

Its meaning: clear bit[4:0] of r0.

2. orr

The format of the ORR instruction is:

ORR{condition}{S} destination register, operand 1, operand 2

The ORR instruction is used to perform a logical OR operation on two operands and place the result in the destination register. Operand 1 should be a

Operand 2 can be a register, a shifted register, or an immediate value.

Some of the digits of the number 1.

Instruction example:

ORR R0, R0, #3; This instruction sets bits 0 and 1 of R0 and leaves the rest of the bits unchanged.

orr r0,r0,#0xd3

     0xd3=1101 0111

     Perform an arithmetic OR operation on r0 and 0xd3, and then return the result to r0, that is, set bits [7:6], [4], and [2:0] of r0 to 1.