【stm32f407】Independent watchdog iwdog

Independent watchdog

The independent watchdog of STM32F4 is driven by a dedicated internal 32Khz low-speed clock (LSI), which is still effective even if the main clock fails. It should be noted that the clock of the independent watchdog is an internal RC clock, so it is not an accurate 32Khz, but a variable clock between 15~47Khz. It’s just that when we estimate, we calculate it at a frequency of 32Khz. The watchdog’s requirements for time are not very precise, so some deviations in the clock are acceptable. There are several registers of the independent watchdog related to this section. We will introduce these registers separately. The first is the keyword register IWDG_KR

Write 0xCCCC in the keyword register (IWDG_KR) to start enabling the independent watchdog; the counter starts from its

The reset value 0xFFF counts down. When the counter counts to the end 0x000, a reset signal (IWDG_RESET) is generated.

Whenever 0xAAAA is written to the keyword register IWDG_KR, the value in IWDG_RLR is reset.

Load into the counter to avoid a watchdog reset. The IWDG_PR and IWDG_RLR registers have a write protection function. To modify the values ​​of these two registers, you must first write 0x5555 to the IWDG_KR register. Writing other values ​​to this register will disrupt the order of operations and the register will be protected again. The reload operation (i.e. writing 0xAAAA) will also activate the write protection function. Next, we introduce the prescaler register (IWDG_PR), which is used to set the division coefficient of the watchdog clock, with a minimum of 4 and a maximum of 256. This register is a 32-bit register, but we only use the lowest 3 bits, and the others are reserved bits. The prescaler register is as follows:

After introducing IWDG_PR, let’s introduce the reload register IWDG_RLR. This register is used to store the reload

The value loaded into the counter. This register is also a 32-bit register, but only the lower 12 bits are valid, as shown in the figure

As long as the above three registers are set accordingly, we can start the independent watchdog of STM32F4.

The watchdog-related library function operation functions are in the file stm32f4xx_iwdg.c and the corresponding header file stm32f4xx_iwdg.h

2. Independent watchdog application

1) Cancel register write protection (write 0X5555 to IWDG_KR)

Through this step, we cancel the write protection of IWDG_PR and IWDG_RLR, so that these two registers can be operated later to set the values ​​of IWDG_PR and IWDG_RLR. The implementation function in the library function is:

IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);

This function is very simple. As the name suggests, it turns on/off write protection, that is, enables/disables write permission.

2) Set the pre-scaling coefficient and reload value of the independent watchdog. The function for setting the pre-scaling coefficient of the watchdog is:

voidIWDG_SetPrescaler(uint8_t IWDG_Prescaler); //Set IWDG prescaler value

The function that sets the reload value of the watchdog is:

voidIWDG_SetReload(uint16_t Reload); //Set IWDG reload value

By setting the watchdog frequency division coefficient prer and reload value, you can know the watchdog feeding time (that is, the watchdog overflow time). The time is calculated as follows:

All=((4×2^prer)×rlr) /40

Where Tout is the watchdog overflow time (in ms); prer is the watchdog clock prescaler value (IWDG_PR value) ranging from 0 to 7; rlr is the watchdog reload value (IWDG_RLR value);

For example, if we set the prer value to 4 and the rlr value to 625, we can get Tout=64×625/40=1000ms. In this way, the overflow time of the watchdog is 1s. As long as you write 0XAAAA to IWDG_KR once within one second, the watchdog will not be reset (of course, writing multiple times is also possible). Here we need to remind you that the watchdog clock is not an accurate 40Khz, so it is best not to feed the watchdog too late, otherwise, the watchdog may be reset.

3) Reload the count value to feed the dog (write 0XAAAA to IWDG_KR)

The function that reloads the count value in the library function is:

IWDG_ReloadCounter(); //Reload the IWDG counter according to the value of the IWDG reload register

Through this sentence, the STM32 will reload the value of IWDG_RLR into the watchdog counter, that is, the feeding operation of the independent watchdog is realized.

4) Start the watchdog (write 0XCCCC to IWDG_KR)

The function to start an independent watchdog in the library function is:

IWDG_Enable(); //Enable IWDG

This sentence is used to start the watchdog of STM32F4. Note that once IWDG is enabled, it cannot be turned off! If you want to turn it off, you can only restart it, and you cannot turn on IWDG after restarting, otherwise the problem will still exist. So here I remind you that if you don't use IWDG, don't turn it on to avoid trouble.

Through the above 4 steps, we can start the watchdog of STM32F4. After enabling the watchdog, the watchdog must be fed at a certain interval in the program, otherwise the program will be reset. Taking advantage of this, we will use an LED light to indicate whether the program is restarted in this chapter to verify the independent watchdog of STM32F4.

After configuring the watchdog, DS0 will be always on. If the KEY_UP button is pressed, the watchdog will be fed. As long as KEY_UP is pressed continuously, the watchdog will not be reset and DS0 will be always on. Once the watchdog overflow time (Tout) is exceeded and the button is not pressed, the program will be restarted, which will cause DS0 to turn off once.

3. Source code

Iwdog.h

#ifndef_IWDOG_H_H_H

#define_IWDOG_H_H_H

#include"stm32f4xx_iwdg.h"

voidIWDG_Init(u8 prer,u16 rlr);//IWDG initialization

voidIWDG_Feed(void); //Dog feeding function

#endif

Iwdog.c

#include"iwdog.h" 

voidIWDG_Init(u8 prer,u16 rlr)

{

  IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable); //Enable writing to IWDG->PR IWDG->RLR

  IWDG_SetPrescaler(prer); //Set IWDG frequency division coefficient

  IWDG_SetReload(rlr); //Set IWDG reload value

  IWDG_ReloadCounter(); //reload

  IWDG_Enable(); //Enable watchdog

}

voidIWDG_Feed(void)

{

  IWDG_ReloadCounter();//reload

}

Main.c

#include"led.h"

#include"key.h"

#include"delay.h"

#include"uart.h"

#include"exit.h"

#include"iwdog.h"

voidUser_Delay(__IO uint32_t nCount)

{

  while(nCount--)

  {

  }

}

staticint count = 0;

intmain(void)

{

#if 1

 NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); //Set system interrupt priority group 2

  delay_init(168); //Initialize delay function

  LED_Init(); //Initialize LED port

  KEY_Init(); //Initialize the key

  delay_ms(100); //delay 100ms 

  IWDG_Init(4,500); //The frequency division number is 64, the overload value is 500, and the overflow time is 1s

  LED_Operate(LED_GREEN,LED_ON);

  while(1)

  {

    if(KEY_Scan() == KEY_ON)

    {

      IWDG_Feed(); //Feed the dog

    }

    delay_ms(10);

  }

#endif

}