I2C communication timing problem of 89 and 12 microcontrollers

I accidentally discovered this problem while using ADC today and would like to share it with all my friends.

I2CDelay of 89:

#define I2CDelay() {_nop_();_nop_();_nop_();_nop_();}

I2CDelay of 12:

void Delay_us(unsigned char us)

{

    do {

        _nop_();

        _nop_();

        _nop_();

        _nop_();

        _nop_();

        _nop_();

        _nop_();

        _nop_();

    } while (--us);

}

I2CDelay(5);

I2C communication is divided into low-speed mode 100kbit/s, fast mode 400kbit/s and high-speed mode 3.4Mbit/s. Because all I2C devices support low speed, but not necessarily the other two speeds, so as a general I2C program, we choose 100k rate to implement, that is to say, the timing generated by the actual program must be less than or equal to the timing parameters of 100k, which obviously requires that the high and low levels of SCL should not be shorter than 5us, so we insert the I2CDelay() bus delay function in the timing function (it is actually 4 NOP instructions, defined at the beginning of the file with define), plus at least one cycle occupied by the statement itself to change the SCL value, to achieve this speed limit.

The 89 routine uses a 11.0592M crystal oscillator. 

12/11059200 is definitely larger than the 1us machine cycle of the 12M crystal oscillator, so the delay of 89 is greater than 4, plus the statement execution time is definitely greater than 5us