PC network experiment platform composed of single chip microcomputer and CS8900A-EEWORLD

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LAN technology is developing very rapidly, and Ethernet is currently the most widely used LAN technology. Therefore, learning Ethernet technology is very important for in-depth mastery of LAN knowledge. The course "Computer Network" is a computer and communication course offered by university computer and related majors. This course is very practical, and many teaching contents require a high-cost experimental environment to be implemented. In addition, network equipment is updated quickly and the cost is high, which is difficult for general universities to afford. Through software technology, establishing a software-simulated laboratory environment can not only save experimental costs, but also improve the level and quality of experimental teaching.

The purpose of this design is to use the embedded network module to realize the sending and receiving of network data, so that students can become familiar with the data sending process of the network.

1 Hardware Design of Experimental Platform

The hardware block diagram of the computer network experiment platform is shown in Figure 1. It is mainly composed of C805lF310, CS8900A, MAX232 and peripheral circuits.

1.1 Single-Chip Microcomputer C8051F310

C8051F310 is a product of Cygnal Corporation of the United States. This device is a fully integrated mixed-signal system-on-chip MCU chip, which is packaged in a 32-pin LQFP package and is small in size. The analog peripherals of C8051F310 include a 10-bit ADC and two analog comparators with a rate of up to 200 KSpS. The supply voltage of the device is 2.7~3.6 V, the typical operating current is 5mA@25MHz, and the typical shutdown current is 0.1μA. At the same time, C8051F310 also has 1280 bytes of internal data RAM (1 K+256) and 16 KB of flash memory, which can be programmed in the system with a sector size of 512 bytes. The digital peripherals of this MCU chip include 29 port I/Os, all port lines have a voltage resistance of 5 V, and have 4 general-purpose 16-bit counters/timers. The clock source of C8051F310 can be either an internal programmable oscillator (24.5 MHz, ±2% accuracy), an external oscillator (crystal, RC, C) or an external clock.

1.2 Ethernet control chip CS8900A

CS8900A is a low-power 16-bit Ethernet controller produced by Cirrus Logic. It is powerful and its highly integrated design eliminates the need for expensive external devices required by other Ethernet controllers. The internal structure of CS8900A is shown in Figure 2.

The CS8900A includes on-chip RAM, 10BASE-T transmit and receive filters, and a direct ISA bus interface with 24 mA drive capability. In addition to its high level of integration, the CS8900A also offers other performance and configuration options. Its unique PacketPage architecture automatically adapts to changes in network traffic patterns and existing system resources, resulting in high system efficiency.

The internal function of CS8900A is mainly 802.3 media access control block (MAC). 802.3 media access control block can support full-duplex operation and can handle the transmission and reception of Ethernet data frames in full accordance with IEEE802.3 Ethernet standard, including collision detection, frame header generation and detection, CRC check code generation and verification, etc. Through the initialization configuration of the transmission controller (TXCMD), MAC can automatically complete the retransmission of the frame after the collision. If the data part of the frame is less than 64 bytes, it can also generate a padding field to make the data frame reach the minimum length required by 802.3.

The main features of CS8900A are that it complies with IEEE802.3 Ethernet standard and has ISA interface. There is 4K bytes of RAM on the chip, which can be used in I/O operation mode, memory operation and DMA operation mode. The chip has a 10BASE-T connection port for transmitting and receiving low-throughput rate, and supports AUI interface of 10BASE2, 10BASE5 and 10BASE-F. It can also automatically generate headers, automatically perform CRC checks, and automatically resend after conflicts. The maximum current consumption of CS8900A is 55 mA (5 V power supply), and it can operate in full duplex mode, while supporting external EEPROM.

After receiving the data packet sent by the host (from the destination address field to the data field, as shown in Figure 3), CS8900A can monitor the network line. If the line is busy, it will wait, otherwise it will send the data frame immediately. Figure 3 shows its 802.3 frame format.

When sending, first add the Ethernet frame header (including the leading field and the frame start flag), then generate the CRC check code, and finally send the data frame to the Ethernet. When receiving, the data frame received from the Ethernet is decoded, the frame header and address are removed, and the data is placed in the cache. In this way, after the CRC check passes, according to the initialization configuration, the CS8900A notifies the host that the data frame has been received, and transmits the data to the host's storage area using a certain transmission mode.

1.3 Hardware circuit analysis and design

This experimental platform uses C805lF310 as the controller, and the Ethernet control chip CS8900A is also a major working component, used to complete the sending and receiving of network data. The network isolation transformer E2023 is used in conjunction with the chip CS8900A to isolate the external line from the CS8900A to prevent interference and realize the live plug-in function. In addition, the CS8900A has two interfaces, one is the RS232 serial interface used to connect to the user module (using the MAX232 chip for level conversion), and the other is the RJ45 interface used to connect to the network.

C8051F310 is connected to CS8900A through data line, address line and control line. It can realize the control and read and write operation of CS8900A's working mode through etc. When CS8900A has hardware reset or software reset, it will default to 8-bit working mode. This design adopts 8-bit mode, so that the P1 port of C8051F310 is connected to the lower 8-bit data line of CS8900A. The data transmission between CS8900A and C8051F310 adopts the default I/O mode, so the read and write pins are set high to close the memory mode. In this mode, 3 address lines can be used to access all registers, as long as the pins SA1, SA2 and SA3 are connected to the address lines of C8051F310. In fact, except for setting SA8 and SA9 high to ensure the default offset address (0X300H), the rest of the unused address lines are connected to low level.

2 Software Design of Experimental Platform

The software part of this system mainly includes computer programs, microcontroller programs and drivers of Ethernet chip CS8900A.

2.1 Computer Programs

The computer program mainly refers to the experimental interface. This is the window of human-computer interaction. Through this interface, students can control and view the sending and receiving processes. In this way, when sending data, they can enter the content to be sent, select the protocol to be used, and control the sending process, and then view and analyze the data at each layer; when receiving data, they can analyze the protocol used by analyzing the received data packets.

2.2 CS8900A driver design

In 8-bit I/0 mode, CS8900A does not support interrupt mode. Therefore, C805lF310 uses query mode to communicate with CS8900A. Before CS8900A starts working, the system must be initialized to determine its working mode. In the process of exchanging data between the host and the network, it is also necessary to continuously read and write the internal registers of CS8900A. Usually in I/0 mode, MCU can read and write all internal registers in CS8900A by operating several main registers of CS8900A. These main working registers are:

LINECTL (0112H): It can determine the basic configuration and physical interface of CS8900A. Its initial value is 00d3H, which can select the physical interface as 10BASE-T and enable the sending and receiving control bits of the device:

RXCTL (0104H): Controls CS8900A to receive specific datagrams. The initial value is 0d05H, which can receive broadcasts on the network or correct datagrams whose target address is the same as the local physical address:

RXCFG (0102H): can control CS8900A to receive specific datagrams and cause interrupts. Can be set to 0103H:

BUSCT (0116H): Controls some operations of the I/O interface of the chip. Set the initial value to 8017H, which can turn on the interrupt control bit of CS8900A:

ISQ (0120H): ISQ is the interrupt status register of CS8900A, which can internally map the contents of the receive interrupt status register and the transmit interrupt status register:

PORTO (0000H): When sending and receiving data, MCU transfers data through PORT0;

TXCMD (0004H): It is the transmit control register. If the data 00COH is written, the CS8900A will start to transmit data after all the data is written.

TXLENG (0006H): Send data length register. When sending data, first write the send data length, and then write the data to the chip through PORT0.

The number in brackets after the register is the offset of the register address relative to the base address 0300H. It should be noted that before initializing the CS8900A, it is necessary to force it into 16-bit mode. During an interrupt processing, the host must continuously read and process the interrupt status queue (ISQ). When an interrupt occurs, the interrupt pin signal becomes high, and the contents of the five registers are mapped to the ISQ in turn until OX000 is read from the ISQ. The software flow chart of its driver is shown in Figure 4.

2.3 MCU (C8051F310) main control program

Usually, C8051F310 will first initialize the chip CS8900A. The initialization part mainly completes the software reset and checks whether the reset completion flag is set; then sets the 8/16-bit working mode, the default is 8-bit mode; then sets the temporary Ethernet physical address (the real address needs to be applied to the authority), and then sets the type of received frame, generally to be able to receive broadcasts, and then determines the data transmission direction (can be set to full-duplex or half-duplex), then allows interrupts, enables receive interrupts, determines the interrupt pin number of CS8900A (determined according to the use of the hardware line), and finally enables receiving and sending.

When C8051F310 completes data unpacking and packing, it will receive datagrams from the network and analyze the datagrams. If it is an IP data packet, it will parse the IP packet and send it to the TCP layer, and send it to the application layer after parsing the TCP segment, and then unpack the data and output it through the serial port. Conversely, if C8051F310 receives data from the serial port, it will pack the data according to the TCP protocol format, and send it to CS8900A after generating IP packets, and then CS8900A will output the data to the LAN.

It can be seen that the link layer is completed by CS8900A, while the network layer and transport layer of TCP/IP are processed by C8051F310, and the application layer is processed by the user according to the needs.

This paper presents the design method of a computer network experimental platform based on the C8051F310 single-chip microcomputer and the CS8900A Ethernet controller. Through this experimental platform, students can complete the relevant experimental content of protocol analysis, thereby enhancing students' understanding of the TCP/IP protocol family.

Keywords：C805lF310 CS8900A MAX232 Reference address：PC network experiment platform composed of single chip microcomputer and CS8900A

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