Analysis of exceptions, interrupts and events in STM32

1 Exceptions and interrupts (Cortex-M3)

1.1 Exceptions and Interrupts

Exact words: 

The Cortex-M3 is equipped with an exception response system at the core level, supporting a large number of system exceptions and external interrupts. 

Among them, numbers 1-15 correspond to system exceptions, and numbers greater than or equal to 16 are all external interrupts. 

Except for some individual exceptions whose priorities are fixed, the priorities of other exceptions are programmable. 

Any event that interrupts the normal flow of execution is called an exception.

The concept of exceptions contains the concept of interrupts, i.e., interrupts are a subset of exceptions.

Both exceptions and interrupts are supported by hardware.

Exception table: 

External interrupt table: 

The "external interrupt" here does not refer to the EXTI interrupt in STM32, but all interrupts.

1.2 Priority

In principle, CM3 supports 3 fixed high priorities and up to 256 levels of programmable priorities, as well as 128 levels of preemption priorities and 128 levels of sub-priorities. However, each manufacturer will make adjustments.

Preemption priority means that a high preemption priority task can interrupt the executing low preemption priority task and allow the CPU to execute the high preemption priority task instead.

When multiple tasks with the same preemption priority but different sub-priorities request an exception at the same time, the CPU will execute the task with the higher sub-priority first.

Preemption priority is also called "preemption priority".

"Sub-priority" is also called "response priority" or "sub-priority".

There is a register in NVIC called "Application Interrupt and Reset Control Register", which has a bit field called "Priority Group".

Priority group assignment: (default is 7-bit preemptive) 

The configuration of the interrupt priority group is usually set once at the beginning of the program. (I have not tried to change the interrupt priority group midway)

1.3 Interruption and Suspension

When the interrupt input pin is asserted (confirmed to be valid?), the interrupt is suspended. Even if the interrupt source cancels the interrupt request later, the interrupt that has been marked as suspended is also recorded. When it reaches the highest priority in the system, it will be responded to. 

However, if the pending state of an interrupt is cleared before it is serviced (for example, software clears the pending state flag while PRIMASK or FAULTMASK is set), the interrupt is canceled. 

When the service routine of an interrupt begins execution, the interrupt is said to enter the "active" state, and its pending bit is automatically cleared by the hardware.

When the interrupt input pin is valid, the interrupt is suspended and will be executed even if the request is canceled.

Whether the interrupt is in a suspended state is the key to whether the interrupt request is responded to.

If the request is presented in a pulsed manner before the interrupt response, it is only regarded as one request (assuming that the suspension is not cleared by software). 

When the interrupt is serviced, the hardware clears the pending state.

During the interrupt response, the request is released, but when it becomes valid again, it will be suspended again. 

After the interrupt response is completed, if the interrupt request still exists, it will be suspended again and wait for a response. 

1.4 SVC and PendSV

SVC (System serVice Call): system (service) call;

SVC exceptions must be responded to immediately. If the priority is not higher than the currently being processed or if it cannot be responded to immediately for other reasons, it will be reported as a hard fault.

PendSV (Pend System serVice): can suspend system calls.

PendSV is different, it can be suspended like a normal interrupt. 

The typical use case for PendSV is during context switching (switching between different tasks).

It is mostly used in operating system software development. (PendSV is used in uC/OS-II to implement task scheduling)

Simple scheduling method: 

1. SysTick 

2. Make a system call (PendSV is set to the lowest priority) 

Task A calls SVC to request a task switch (e.g., to wait for some work to complete)

The OS receives the request, prepares for the context switch, and pends a PendSV exception.

When the CPU exits SVC, it immediately enters PendSV, thereby performing a context switch.

When PendSV is executed, it will return to task B and enter thread mode.

An interrupt occurs and the interrupt service routine begins execution

During the execution of the ISR, a SysTick exception occurs and the ISR is preempted.

The OS performs the necessary operations and then raises a PendSV exception to prepare for the context switch.

When SysTick exits, it returns to the previously preempted ISR, and the ISR continues to execute.

After the ISR is executed and exits, the PendSV service routine begins execution and performs context switching in it.

When PendSV is executed, it returns to task A and the system enters thread mode again.

1.5 CM3 Interrupt Processing Features——Tail-Chainign

When two interrupts of the same priority level are connected, breakpoint recovery and breakpoint data recovery are not performed, and execution is directly transferred to the next interrupt.

2 Interrupts and events (to be continued)

In the figure: 

The interrupt/event first undergoes edge detection to confirm that an interrupt/event request has occurred, and is "ORed" with the software interrupt/event register. The request pending register records that an interrupt/event request has occurred, and then a branch occurs:

1. Interrupt: ANDed with the interrupt mask register and transferred to the NVIC controller for control. 

2. Event: ANDed with the event mask register to generate a pulse.