STM32 M0 clock configuration

This article mainly talks about the clock configuration of STM32 M0.

Let's first look at the clock tree of the M0 core (stm32f072)

As can be seen from the figure, the M0 chip has 4 clock sources, a high-speed internal RC clock source with a frequency of 8M; a high-speed external clock source with a frequency of 8 to 32MHz; a low-speed external clock source with a frequency of generally 32.768kHz; a low-speed internal clock source with a frequency of 40kHz;

1. HSI

When the chip is powered on, the internal RC oscillation is enabled by default, that is, the internal clock source of 8MHz. If the clock requirement is not very high, using the internal clock is sufficient, saving the money for an external crystal oscillator.

Let's first talk about the configuration of using the internal clock. The official demo uses the internal clock by default. Let's start with the clock tree analysis, HSI (8MHz) startup, through PLLSRC (phase-locked loop clock source selection register), and then to PREDIV (prescaler), the prescaler selects no frequency division, and then PLLMUL (phase-locked loop multiplier), here the frequency is multiplied by 6 times, and the frequency is 48MHz. Be careful not to exceed 48MHz, the maximum supported by the chip is 48MHz. Then SW (clock source selection register), here select PLLCLK (phase-locked loop clock after multiplication), in fact, here you can directly select the 8MHz internal clock, not PLLCLK. The final choice of SW is our machine clock.

II. HSE

HSE means high-speed external clock. In order to obtain a lower temperature drift and a more stable clock, an external crystal oscillator is generally selected. If an external crystal oscillator is added, the external clock selection register needs to be turned on, and then the external clock oscillates stably. The stable waiting time needs to be selected according to different oscillation frequencies. After waiting for the external clock to oscillate stably, come to PLLSRC, where HSE is selected. Assuming that the external crystal oscillator is 8MHz, PREDIV is also selected as non-divided, PLLMUL is selected as 6 times frequency, and the clock source is selected as HSE in SW, then the machine clock of the chip is 48MHz.

Observe the SW register, there is a CSS option, which is a clock safety selection register. Its function is to switch to HSI immediately when the external crystal oscillator suddenly stops working. When the program is running, the external crystal oscillator stops oscillating, and the system will immediately switch to the internal clock. At this time, a synchronous abnormal interrupt will be generated, and the interrupt level is negative and cannot be modified. In the interrupt, the HSI frequency is divided and multiplied by itself, and then the main clock is changed to the required machine clock. CSS is only meaningful after HSE is turned on. If the internal clock is used, this option can be ignored. Of course, this option can also be chosen not to be turned on, and it is not turned on by default.

3. LSE

The low-speed external clock also needs to be configured and enabled. After it is enabled and the oscillation is stable, the RTCCLK (real-time clock selection register) selects LSE, which is used to provide a clock source for the internal RTC. As for why it is 32.768kHz, this article does not intend to explain it in detail. Please search on Baidu. LSE can also be used as a machine clock source. I have not tried it, and I believe no one has done it. If you have, please introduce your experience and purpose.

4. LSI

The low-speed internal clock is the internal dedicated clock that provides the internal watchdog register. The watchdog time setting is on this clock line. The watchdog time is generally selected in seconds. My opinion is that the longer the time, the better. One thing to note about the use of the watchdog is that whether it is bare-metal development or development with RTOS, the watchdog cannot be fed in an interrupt. The entire code can and can only have one place to feed the watchdog. Of course, if you insist on feeding the watchdog once in the infinite loop of tasks A, B, and C, that's fine, but if the reader really adopts this approach, it is recommended to seriously think about whether there is room for improvement in the software architecture.

5. I2C1

The I2C interface clock can be selected from HSI or machine clock

6. I2S

I2S can only select the machine clock

VII. AHB

The basic peripheral clock source pre-divides the machine clock to obtain the required frequency and supplies it to the peripherals on the AHB bus according to the needs. DMA, SRAM, FLITFEN, CRC, GPIO, TSC and other peripherals are directly mounted on this clock bus. After the division, there is another way to supply APB, which also has a pre-divider, and USART and TIM are mounted. The clock source selection of USART is relatively rich. You can choose PCLK from APB, or directly select the machine clock, HSI, LSE, etc.; TIM clock also has a pre-divider, called APB1, the purpose is to obtain the required timing time or pulse width frequency.

The basic clock of STM32M0 is basically finished here. At first glance, this clock diagram is still quite complicated, just like when learning analog circuits, directly taking the schematic diagram of the switching power supply to look at it is like reading a book of heaven, but if you can calm down and chew it bit by bit, you can still slowly understand it. Recently, various chip manufacturers have developed their own code generation tools, which are much more convenient for development and lower the development threshold. However, if you can have a deep understanding of the chip (of course, you don’t have to go deep into the IP layer), when problems occur, DEBUG can be faster. To borrow a sentence from Song Baohua: Sooner or later, you will have to pay back for what you have done. What you don’t understand today but are unwilling to understand, when the problem reappears in the future, it is time to pay back.