STM32F103_USART_GPIO configuration and corresponding IO port settings

STM32 series microcontroller GPIO data collection and summary

1. GPIO Configuration

(1)GPIO_Mode_AIN analog input

(2)GPIO_Mode_IN_FLOATING Floating input

(3)GPIO_Mode_IPD pull-down input

(4)GPIO_Mode_IPU pull-up input

(5)GPIO_Mode_Out_OD open drain output

(6)GPIO_Mode_Out_PP push-pull output

(7)GPIO_Mode_AF_OD Multiplexed open-drain output

(8)GPIO_Mode_AF_PP Multiplexed push-pull output

GPIO_Speed_10MHz Maximum output rate 10MHz

GPIO_Speed_2MHz Maximum output rate 2MHz

GPIO_Speed_50MHz Maximum output rate 50MHz

1.1 There are 3 output speeds to choose from in the I/O port output mode (2MHz, 10MHz and 50MHz). This speed refers to the I/O port drive circuit.

Response speed rather than output signal speed,

***The speed of the output signal is related to the program***

(The chip has multiple I/O ports in the output section.

The output drive circuit has different response speeds. Users can choose the appropriate drive circuit according to their needs.

The output drive module can achieve the best noise control and reduce power consumption. The high-frequency drive circuit has high noise.

When outputting a high frequency signal, please select a low frequency drive circuit, which is very helpful to improve the EMI performance of the system.

However, if a lower frequency driver module is selected, a distorted output signal may be obtained.

The key is to match the GPIO pin speed to the application (recommended 10 times or more?). For example:

1.1.1 For the serial port, if the maximum baud rate is only 115.2k, then a 2M GPIO pin speed is sufficient, which saves power and reduces noise.

1.1.2 For the I2C interface, if you use a 400k baud rate, if you want to leave more margin, then using a 2M GPIO pin speed may not be enough.

At this time, you can choose a GPIO pin speed of 10M.

1.1.3 For the SPI interface, if you use 18M or 9M baud rate, the 10M GPIO pin speed is obviously not enough, you need to use 50M

The pin speed of the GPIO.

1.2 When the GPIO port is set as input, the output drive circuit is disconnected from the port, so the output speed configuration is meaningless.

1.3 During reset and immediately after reset, the multiplexing function is not enabled and the I/O ports are configured in floating input mode.

1.4 All ports have external interrupt capability. In order to use the external interrupt line, the port must be configured in input mode.

1.5 The GPIO port configuration has a locking function. After the GPIO port is configured, the configuration combination can be locked through the program until the next chip reset.

To unlock it.

2. The difference between push-pull output and open-drain output

Push-pull output: can output high and low levels, connect digital devices; open-drain output: the output end is equivalent to the collector of the transistor. To get a high level state

The pull-up resistor is required for the state. It is suitable for current-type driving and has a relatively strong ability to absorb current (generally within 20ma).

The push-pull structure generally refers to two transistors being controlled by two complementary signals, and one transistor is always turned on while the other is turned off.

To realize line-and, an OC (open collector) gate circuit is required. It is two transistors or MOSFETs with the same parameters that exist in the circuit in a push-pull manner.

In the circuit, each is responsible for the waveform amplification task of the positive and negative half cycles. When the circuit is working, only one of the two symmetrical power switch tubes is turned on at a time, so the conduction

Low loss and high efficiency. The output can both sink current to the load and extract current from the load.

When the port is configured as output: Open drain mode: When outputting 0, N-MOS is turned on, P-MOS is not activated, and output is 0.

When outputting 1, N-MOS is high impedance, P-MOS is not activated, and output is 1 (external pull-up circuit is required); this mode can use the port as a bidirectional IO

use.

Push-pull mode: When the output is 0, N-MOS is turned on, P-MOS is high impedance, and the output is 0.

When outputting 1, N-MOS is high impedance, P-MOS is turned on, and output is 1 (no external pull-up circuit is required).

Simply put, when the open drain is 0, it is connected to GND, and when it is 1, it is floating. When the push-pull is 0, it is connected to GND, and when it is 1, it is connected to VCC.

3. Select IO mode in STM32

(1) Floating input_IN_FLOATING——Floating input, can be used for KEY identification, RX1

(2) Pull-up input_IPU——IO internal pull-up resistor input

(3) Pull-down input_IPD——IO internal pull-down resistor input

(4) Analog input_AIN - Use ADC analog input or save power in low power consumption

(5) Open-drain output_OUT_OD——IO output 0 is connected to GND, IO output 1 is left floating and requires an external pull-up resistor to achieve a high output level.

When the output is 1, the state of the IO port is pulled high by the pull-up resistor, but because it is an open-drain output mode, the IO port can also be switched by an external

The IO input level change can be read to realize the IO bidirectional function of C51.

(6) Push-pull output_OUT_PP ——IO output 0 - connected to GND, IO output 1 - connected to VCC, the read input value is unknown

(7) Multiplexed function push-pull output _AF_PP - on-chip peripheral function (SCL, SDA of I2C)

(8) Multiplexed function open-drain output _AF_OD - on-chip external functions (TX1, MOSI, MISO.SCK.SS)

Example summary:

(1) Use open-drain output _OUT_OD to simulate I2C, connect a pull-up resistor, and it can correctly output 0 and 1; when reading the value, first

GPIO_SetBits(GPIOB, GPIO_Pin_0); pull high, then you can read the value of IO; use

GPIO_ReadInputDataBit(GPIOB,GPIO_Pin_0);

(2) If there is no pull-up resistor, IO is high level by default; if you need to read the value of IO, you can use

With pull-up input_IPU and floating input_IN_FLOATING and open-drain output_OUT_OD;

4. IO low power consumption:

Regarding analog input & low power consumption, according to the STM32 low power consumption AN (AN2629) and its source file, in STOP mode, in order to get the lowest possible

To reduce power consumption, set all IO (including non-A/D input GPIO) to analog input.

5. Procedure

(1) Clock:

RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |

RCC_APB2Periph_GPIOC, ENABLE);

(2)IO configuration:

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; // IR input

GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;GPIO_Init(GPIOC, &GPIO_InitStructure);

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_15;

GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;

GPIO_Init(GPIOB, &GPIO_InitStructure);

(3) Input and output:

Output 0: GPIO_ResetBits(GPIOB, GPIO_Pin_0)

Output 1: GPIO_SetBits(GPIOB, GPIO_Pin_0)

输入: GPIO_ReadInputDataBit(GPIOB,GPIO_Pin_7)

***

Simply put, when the open drain is 0, it is connected to GND, and when it is 1, it is floating. When the push-pull is 0, it is connected to GND, and when it is 1, it is connected to VCC.

----------------------------------------------------

***

About the level status of the I/O port at the moment of STM32 power-on reset

When the STM32 is powered on and reset, the default level state of the I/O port is floating input, so it is high impedance. This achieves low power consumption.

The IO pin configuration port of STM32 is configured as floating input by default, leaving the choice to the user. This is a great advantage: on the one hand, floating input ensures

There will be no default level that the user does not want (the level depends on the user's peripheral circuit); on the other hand, the power consumption is reduced because no matter whether it is on

From another perspective, no matter what the default configuration of the I/O pin is, it is still necessary to set the output pin to the same current.

The pin is pulled up or down to ensure that the output pin is always at a known level during chip power-on and reset.

─ Input floating

─ Input pull-up

─ Input pull-down

─ Analog input

─ Open drain output

─ Push-pull output

─ Push-pull multiplexing function

─ Open drain multiplexing function

After the IO port is reset, it is in a floating state, that is, its level state is determined by the peripheral circuit. This is very important if you are designing industrial products.

It must be determined;

IO pins are compatible with 5V power supply;

Why don't stm32 serial ports 1, 2, 3, 4, and 5 work?

Please pay attention to some general issues, such as:

There is a conflict between UART3 and SPI2, so the SPI clock must be turned off.

After carefully analyzing the program, the most likely cause is rcc. I turned them all on and debugged them one by one. I found

RCC_APB1Periph_I2C1,RCC_APB1Periph_I2C2 enable causes usart3 to be abnormal, RCC_AHBPeriph_SDIO enable causes

usart4 is abnormal, I thought it might be a pin conflict, I opened the pin definition, haha, it is indeed the case.

usart1 is APB2, USART2,3,UART4,5 are all APB1, there is no mistake about this.

Generally speaking, the code should handle the following parts:

1)RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);

RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE);

2)NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);

NVIC_InitStructure.NVIC_IRQChannel = UART4_IRQChannel;

NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;

NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;

NVIC_Init(&NVIC_InitStructure);

3)/* Configure UART4 Rx (PC.11) as input floating */

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;

GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;

GPIO_Init(GPIOC, &GPIO_InitStructure);

/* Configure UART4 Tx (PC.10) as alternate function push-pull */

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;

GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;

GPIO_Init(GPIOC, &GPIO_InitStructure);

4)USART_InitStructure.USART_BaudRate = 115200;

USART_InitStructure.USART_WordLength = USART_WordLength_8b;

USART_InitStructure.USART_StopBits = USART_StopBits_1;

USART_InitStructure.USART_Parity = USART_Parity_No;

USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;

USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;

5)USART_Init(UART4, &USART_InitStructure);

/* Enable USART4 Receive and Transmit interrupts */

USART_ITConfig(UART4, USART_IT_RXNE, ENABLE);

/* Enable the USART4 */USART_Cmd(UART4, ENABLE);

STM32 UART usage process

1. Before using UART, the corresponding peripheral clock must be started, which mainly uses the RCC_APBnPeriphClockCmd function of the firmware library.

Enable UART1: use RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1,ENABLE)

Enable UART2: use RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE)

2. To use interrupts for UART operations, you need to configure NVIC and set the interrupt priority. For example:

/* Configure the NVIC Preemption Priority Bits */

NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);

/* Enable the USART1 Interrupt */

NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQChannel;

NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;

NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;

NVIC_Init(&NVIC_InitStructure);

3. Configure the corresponding GPIO port.

If the system's UART needs to be remapped, you need to use the GPIO_PinRemapConfig function to remap it, such as:

GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; //Note: Rx is floating, Tx is the second function pull-up.

Configure Rx to floating input mode and Tx to the second power mode with pull-up. And initialize with GPIO_Init() function. For example:

/* Configure USART2 Rx PA3 input floating */

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;

GPIO_Init(GPIOA, &GPIO_InitStructure);

/* Configure USART1 Tx (PA.09) as alternate push-pull */

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;

GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;

GPIO_Init(GPIOA, &GPIO_InitStructure);

4. Configure UART

After configuring the correct external crystal oscillator in the conf file, directly write the UART baud rate,

Communication frame, mode, hardware communication control, transceiver mode. Then use USART_Init() to initialize. For example:

USART_InitStructure.USART_BaudRate = 9600;

USART_InitStructure.USART_WordLength = USART_WordLength_8b;

USART_InitStructure.USART_StopBits = USART_StopBits_1;

USART_InitStructure.USART_Parity = USART_Parity_No;

USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;

USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;

/* Configure USART1 */

USART_Init(USART1, &USART_InitStructure);

Then enable the transmit and receive interrupts. For example:

/* Enable USART1 Receive and Transmit interrupts */USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);

USART_ITConfig(USART1, USART_IT_TXE, ENABLE);

// USART_ITConfig(USART1, USART_IT_TXE, DISABLE);

Note: Generally, the TXE interrupt is not enabled. Once this interrupt is enabled, if the UART transmit buffer is empty, the UART will immediately enter the

Therefore, you can enable TXE interrupt when you need to send data in the program. Use USART_SendData() to send data in UART interrupt.

according to.

After enabling the interrupt, you also need to enable the UART port:

like:

/* Enable the USART1 */

USART_Cmd(USART1, ENABLE);

/* Enable the USART2 */

USART_Cmd(USART2, ENABLE);

The interrupt program (stm32f10x_it.c) can be sent as follows: Note that all serial port interrupts need to be judged in the interrupt service program

Sources are processed separately.

void USART1_IRQHandler(void)

{

if(USART_GetITStatus(USART1, USART_IT_RXNE) != RESET)

{

/* Read one byte from the receive data register */

RxBuffer1[RxCounter1++] = USART_ReceiveData(USART1);

if(RxCounter1 == NbrOfDataToRead1)

{

USART_ITConfig(USART1, USART_IT_RXNE, DISABLE); //After sending, disable RXNE.

}

}

if(USART_GetITStatus(USART1, USART_IT_TXE) != RESET)

{

USART_SendData(USART1, TxBuffer1[TxCounter1++]);

if(TxCounter1 == NbrOfDataToTransfer1)

{

USART_ITConfig(USART1, USART_IT_TXE, DISABLE);

}

}

}

void USART1_IRQHandler(void)

{

if(USART_GetITStatus(USART1, USART_IT_RXNE) != RESET)

{

/* Read one byte from the receive data register */

RxBuffer1[RxCounter1++] = USART_ReceiveData(USART1);

if(RxCounter1 == NbrOfDataToRead1)

{

USART_ITConfig(USART1, USART_IT_RXNE, DISABLE); //After sending, disable RXNE.

}

}

if(USART_GetITStatus(USART1, USART_IT_TXE) != RESET)

{

USART_SendData(USART1, TxBuffer1[TxCounter1++]);

if(TxCounter1 == NbrOfDataToTransfer1)

{

USART_ITConfig(USART1, USART_IT_TXE, DISABLE);

}

}

}

STM32 UART summary

The interface is connected to other external devices through 3 pins.

Any USART bidirectional communication requires at least two pins: receive data input RX and transmit data output TX

When the transmitter is disabled, the output pin reverts to the I/O port configuration. When the transmitter is enabled and no data is being sent, the TX pin is high.

The word length can be selected as 8 or 9 bits by setting the M bit in the USART_CR1 register.

The TX pin is low during the start bit and high during the stop bit.

The idle character is considered to be a frame of all "1s", followed by the start bit of the next frame containing data (the number of "1s" includes the stop bit).

Number of)

The gap character is considered to be a frame period with all "0" received. After the gap frame, the transmitter inserts 1 or 2 stop bits (logic "1").

To answer the start bit

Transmitter

The transmitter can send 8 or 9-bit data words, depending on the state of the M bit. The associated clock pulse is output on the SCLK pin.

1. Character sending

During USART transmission, the least significant bit appears first on the TX pin. In this mode, the USART_DR register contains an internal bus and transmit shift register.

Each character is preceded by a logic low start bit and ends with a programmable number of stop bits.

After the TE bit is enabled, an idle frame will be sent.

2. Configurable stop bits

1 stop bit: This is the number of stop bits for the stranger

2 stop bits: regular USART, supported in single-wire and modem modes

0.5 stop bit: used when receiving data in smart card mode

1.5 stop bits: used when sending data in smart card mode

The idle frame transmission includes the stop bit.

The gap frame is 10 (11) low bits followed by the configured stop bits.

Configuration process: Enable USART by writing 1 to the UE bit in the USART_CR1 register->Configure the M bit in the USART_CR1 register to define

Word length->Configure the number of stop bits in the USART_CR2 register->If multi-buffer communication is used, select the DMA enable bit in the USART_CR3 register

(DMAT), configure the DMA registers as explained in Multi-buffered Communication->Set the TE bit in the USART_CR1 register to send an idle frame

As the first transmission -> select the desired baud rate through the USART_BRR register -> write the data to be sent to the USART_DR register,

This will also clear the TXE bit.

3. Single byte communication

Clearing the TXE bit is usually done by writing data into the data register.

TXE is set by hardware, which indicates that data has been transferred from TDR to the shift register and data transmission has begun; the TDR register is

Empty; the next data can be written to the USART_DR register without overwriting the previous data

While transmission is in progress, a write command to the USART_DR register saves the data to the TDR register, and after the current transmission is completed,

The data in the TDR register will be copied into the shift register.

When no transmission is in progress, write a data into the USART_DR register, the data will be directly placed into the shift register, and the transmission starts, TXE

The bit will be set to 1 immediately

When a frame is sent (after the end bit), the TC bit is set to 1.

Clearing the TC bit is accomplished by the following software operations: (1) reading the USART_SR register once (2) writing the USART_DR register once (TC bit is also cleared).

It can be cleared by writing 0 to it. This clearing sequence is only recommended for multi-buffer communication)

4. Gap Character Setting the SBK bit will send a gap character. If the SBK bit is set to 1, a gap character will be sent on the TX line after completing the current transmission.

This bit is reset by hardware when the gap character is sent. The USART inserts a logic 1 at the end of the last gap frame to ensure

The start bit of the next frame can be identified

If the software resets SBK before the gap character is sent, the gap character will not be sent.

5. Idle Symbol

Setting the TE bit will drive the USART to send an idle frame before the first data frame.

receiver

The receiver can receive 8-bit or 9-bit data words, depending on the M bit in the USART_CR1 register.

1. Character reception

During a USART reception, the RX pin receives the least significant bit first. In this mode, the USART_DR register consists of an internal bus and

The buffer between the receive shift register (RDR) is composed

Configuration process: Enable USART by writing 1 to the UE bit in the USART_CR1 register->Configure the M bit in the USART_CR1 register to define

Word length->Configure the number of stop bits in the USART_CR2 register->If multi-buffered communication occurs, select DMA enable in the USART_CR3 register

bit (DMAT) -> select the desired baud rate through the baud rate register USART_BRR -> set RE in the USART_CR1 register, which will enable

The receiver starts looking for the start bit.

When a character is received:

The RXNE bit is set to 1, indicating that the contents of the shift register are transferred to RDR

If the RXNEIE bit is set to 1, an interrupt will be generated

If a frame error, noise or overflow error is detected during reception, the error flag will be set to 1.

In multi-buffered reception, RXNE is set to 1 after each byte is received and cleared by reading the data register via DMA.

In single buffer mode, clearing the RXNE bit is done by software reading the USART_DR register. The RXNE flag can also be cleared by writing 0 to it.

The bit must be cleared before the next character is received, otherwise an overflow error will occur.

2. Space character:

When a gap character is received, USART treats it as a frame error.

3. Idle Symbol:

When an idle frame is received, it will be processed in the same way as data reception. In addition, if the IDLEIE bit is set to 1, an interrupt will be generated.

4. Overflow Error

When a character is received and the RXNE bit has not been reset, an error will occur. Data cannot be shifted out of the

Register transfer to RDR register

When an overflow error occurs, the ORE bit is set to 1. By reading the USART_DR register after reading the USART_SR register, the ORE bit is reset.

When the ORE bit is set to 1, it indicates that at least one data has been lost: If RXNE=1, the last valid data is stored in the receive register RDR and can be

Read; RXNE = 0, the last valid data has been read out, there is no readable data in RDR

5. Noise Error

Noise detected in the frame: NE is set to 1 on the rising edge of the RXNE bit

Invalid data is transferred from the shift register to the USART_DR register

If it is a single-byte communication, no interrupt will be generated; in multi-buffer communication, if the EIE bit in the USART_CR3 register is set to 1, it will cause an interrupt.

Interrupt

The NE bit is reset by reading the USART_SR register and the USART_DR register in sequence.

6. Frame Error

The stop bit was not received and recognized in time with it due to lack of synchronization or excessive noise.

When a frame error is found: the FE bit is set to 1 by hardware; invalid data is transferred from the shift register to the USART_DR register; if it is a single-byte communication,

No interrupt will be generated, but this bit will rise together with the RXNE bit which generates an interrupt itself. In multi-buffered communication, if the EIE bit in the USART_CR3 register is set to 1, an interrupt will be caused.

The NE bit is reset by reading the USART_SR register and the USART_DR register once.

7. Configure stop bits during reception

The number of stop bits to be received can be configured via the control in control register 2. In normal mode it can be 1 or 2 bits.

The mode may be 0.5 bit or 1.5 bit

Fractional Baud Rate Generation

Both the receiver and transmitter (RX and TX) are set to the values ​​configured in the USARTDIV integer and fractional registers.

TX/RX baud rate = Fck/(16*USARTDIV)

Example: Calculate USARTDIV from the value of the BRR register

If DIV_Mantissa=27D,DIV_Fraction=12D(BRR=1BCH), then

Mantissa(USARTDIV)=27D

Fraciton(USARTDIV)=12/16=0.75D

Therefore, USARTDIV = 27.75D

After writing to USART_BRR, the baud rate counter is updated with the new value in the baud rate register, so the baud rate register should not be changed during processing.

Register value

Only USART1 is clocked by PCK2 (maximum 72MHZ), the others are clocked by PCLK1 (maximum 36MHZ)

Multiprocessor Communication

USART can be used for multi-processor communication (just connect multiple USARTs to a network).

Unaddressed devices can be put into silent mode by means of the silent function.

In silent mode: all receive status bits will not be set

All receive interrupts are disabled

The RWU bit in the USART_CR1 register is set to 1. RWU can be automatically controlled by hardware or written by software under certain conditions.

The USART can enter and exit silent mode in two ways: if the WAKE bit is reset, in idle line detection mode

If the WAKE bit is set, the address mark detection mode is used.

1. Idle line detection mode (WAKE=0)

When the RWU bit is written to 1, the USART enters silent mode

When an idle frame is found, the USART exits silent mode and the RWU bit is cleared by hardware, but the IDLE bit in the USART_SR register is not cleared.

Set to 1. RWU can also be cleared to 0 by software

2. Address mark detection (WAKE=1)

In this mode, bytes with MSB 1 are considered addresses, otherwise they are considered data.

When an address character is received that does not match the address pre-set in the ADD bits of the USART_CR2 register, the USART enters silent mode.

When an address character matching the set address is received, USART exits silent mode. RWU is cleared and the following bytes will be received normally.

The RXNE bit will be set to 1 upon receiving an address character.

When there is no data in the receiving buffer (RXNE=0 in the USART_SR register), the RWU bit can be written as 0 or 1, otherwise the write operation will be ignored.

slightly.

Before selecting silent mode (setting the RWU bit), the USART must first receive a data byte, otherwise it cannot operate in the idle line detection mode.

Silent mode for wake-up.

In the address flag detection wake-up configuration (WAKE=1), the RWU bit cannot be modified by software when the RXNE bit is set to 1.

Parity control can be enabled by setting the PCE bit in the USART_CR1 register.

Transmit mode: If the PCE bit of USART_CR1 is set, the data written into the data register is sent out after the MSB bit is replaced by the parity bit.

LIN Mode

This mode is selected by the LINEN bit in the USART_CR2 register. In LIN mode, CLKEN bit, STOP[1:0] bit, SCEN, HDSEL, IREN

Must remain clear

1. LIN transmission

The following differences exist from normal USART transmission: Clear the M bit to set the 8-bit word length; Set the LINEN bit to enter LIN mode. In this case,

Set the SBK bit to send 13 "0"s as gap characters, and then send a "1" to start the actual detection.

2. LIN reception

When LIN mode is enabled, the gap detection circuit is activated. The detection is completely independent of the normal USART receiver.

or during the reception of a frame can be detected

The method for detecting the start bit is the same as that for finding the gap character or data. After finding the start bit, the circuit samples the following bits. If 10 (LBDL = 0) or

If the 11 consecutive bits (LBDL=1) are all 0 and a separator is added, the LBD flag of the USART_SR register is set to 1.

If 1 is sampled before the 10th or 11th sampling, the gap detection circuit cancels the current detection and searches for a start bit again.

LIN mode is enabled. Once a frame error occurs, the receiver will not stop until a "1" is received without the gap word being completed or a gap is detected.

A delimiter is received after the gap

USART Synchronous Mode

Synchronous mode is selected by writing 1 to the CLKEN bit in the USART_CR2 register. In this mode, the following bits must remain clear:

LINEN,SCEN,HDSEL,IREN

The USART allows the user to control bidirectional synchronous serial communication in master mode. The SCLK pin is the output of the USART transmitter clock. The start and stop bits are

No clock pulses are sent to SCLK during the bit period.

The external clock will not be activated during idle time, before the actual data arrives, and during the transmission gap.

SCLK and TX are synchronous, and the data on TX is also synchronous. The USART receiver and asynchronous mode use different working modes. If RE=1, the data

Sampling on SCLK without any oversampling

The SCLK pin works with the TX pin, so the clock is only provided when the transmission is enabled and the data is being sent. This means that it is not possible to

Received synchronous data when no data was sent

LBCL, CPOL, CPHA must be selected when both the transmitter and receiver are disabled. They cannot be changed when the transmitter or receiver is enabled.

It is recommended to set the TE and RE bits in the same instruction to minimize the receiver setup and hold times.

Single-line half-duplex mode

This mode is selected by setting the HDSEL bit in the USART_CR3 register. The following bits must be kept clear in this mode:

LINEN,CLKEN,SCEN,HDSEL,IREN

Once HDSEL is written to 1: RX is no longer used; TX is always released when there is no data transmission. Therefore, it is in idle state or receiving state.

It behaves as a standard I/O port. When not driven by USART, this I/O port must be configured as a floating input or open-drain output high.

In particular, transmission is never blocked by hardware. Once the TE bit is set to 1 and data is written to the data register, transmission will occur continuously.

Smart card mode is selected by setting the SCEN bit in the USART_CR3 register. In this mode, the following bits must be kept clear:

LINEN, HDSEL, IREN

The CLKEN bit may be set to provide a clock to the smart card.

The smart card interface design is to support a smart card protocol defined in the ISO7816-3 standard. The USART should be configured as follows: 8-bit data home parity

Verify that M=1, PCE=1 in the USART_CR1 register and one of the following conditions is met:

0.5 stop bit when receiving: STOP=01 in USART_CR2

1.5 stop bits when sending, STOP=11 in USART_CR2

When connected to a smart card, the TX output of the USART drives a bidirectional line which is also driven by the smart card (SW_RX and TX must be connected to the same I/O).

TX_EN is asserted when sending the start bit and data bytes, and is deasserted when the stop bit is sent. This way, the receiver can only receive parity errors when a parity error occurs.

If TX_EN is not used, TX is pulled high during the stop bit, so the receiver can also

To drive this line

Smart card is a single-line half-duplex communication protocol

Data transmission through the transmit shift register is delayed by at least 1/2 the baud clock

If a parity error is detected when receiving a 1/2 stop bit frame, the transmit line is pulled low and held for one baud clock when the receive frame is completed.

Setting the TC flag to be valid can be delayed by setting the protection time register

The revocation of the TC flag will not be affected by the smart card mode

If the transmitter detects a frame error, NACK will not be treated as a start bit by the transmitter's receiving module.

At the receiver end, if a parity error is detected and a NACK is sent, the receiver does not treat the NACK as a start bit.

In smart card mode, the gap character is meaningless, and the 00H data with frame error is regarded as data instead of the gap character.

When the TE bit is toggled, no idle frames are sent. The ISO protocol does not define idle frames.

The USART can provide a clock to the smart card through the SCLK output bit. In smart card mode, SCLK has nothing to do with communication, but is first output through a 5-bit preset.

The divider simply uses the internal peripheral input clock to drive the smart card clock.

IrDA SIR ENDEC Module

IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In this mode, the following bits must be kept clear:

LINE,STOP,CLKEN,SCEN,HDSEL

The SIR transmit encoder modulates the NRZ bit stream output from the USART. In normal mode, the transmit pulse width is defined as 3/16 bit period.

The SIR receiver decoder receives the zero bit stream from the infrared detector and outputs an NRZ serial bit stream to the USART.

The transmitter output and decoder input have opposite polarity.

IrDA is a half-duplex communication protocol. If the transmitter is busy, the IrDA decoder will ignore all data on the IrDA receive line.

If the device is busy, the data from USART to IrDA on TX will not be encoded by IrDA. When receiving data, avoid sending data, otherwise the data to be sent will be too long.

Data may be destroyed

A "0" is sent as a high pulse, and a "1" is sent as a "0".

The SIR decoder converts the IrDA compatible receive signal into a USART bit stream

The SIR receiving logic interprets the high state as a logic "1" and the low pulse as a logic "0"

The output of the encoder and the input of the decoder have opposite polarity. The output of SIR is low when idle.

The IrDA specification requires that acceptable pulses be greater than 1.41 microseconds, and the acceptable pulse width is programmable.

Receivers can communicate with low-power transmitters

In IrDA mode, the STOP bit in the USART_CR2 register must be set to 1.

The IrDA low power mode is described as follows:

Transmitter: Pulse width is 3 times the low power baud rate. In low power mode, the prescaler value can be set to divide the system clock. Receiver: Similar to receiving in normal mode. The USART should ignore pulses with a width less than 1PSC.

Continuous communication using DMA

The USART can use DMA for continuous communication. The RX and TX buffers can generate DMA requests independently.

1. Use DMA to send

DMA mode transmission can be enabled by setting the DMAT bit in the USART_CR3 register. As long as the TXE bit is set to 1, data can be transmitted through DMA

The peripherals are imported from the configured SARM area into the USART_DR register. Use the following process to map a DMA channel for transmission:

Write the address of USART_DR register to DMA control register and configure it as the target address for transmission. Every time TXE event occurs, data will be transferred from

Memory is transferred to this address

Write the memory address to the DMA control register and configure it as the source address of the transmission. Every time the TXE time occurs, the data will be transferred from this memory.

Area transferred to USART_DR register

Write the total number of bytes to be sent to the DMA control register

Set channel priority in DMA registers

Set up DMA interrupt for half/full transfer according to application needs

Activate channels using DMA registers

When the number of transfers reaches the value set in the DMA control register, the DMA control register generates an interrupt on the DMA channel interrupt vector.

To use DMA to send, do not enable TXEIE

2. Use DMA to receive

DMA mode reception can be enabled by setting the DMAR bit in the USART_CR3 register. As soon as a data byte is received, the data can be received by

The DMA peripheral is imported from the USART_DR register into the configured SARM area. Use the following process to map a DMA for USART reception:

aisle

Write the address of the USART_DR register to the DMA control register and configure it as the target address for transmission. Every time an RXNE event occurs, the data will be

Transfer from this address to memory

Write the memory address to the DMA control register and configure it as the target address for transmission. Every time an RXNE event occurs, data will be transferred from USART_DR

Registers are transferred to this memory area

Write the total number of bytes to be sent to the DMA control register

Set channel priority in DMA registers

Set up DMA interrupt for half/full transfer according to application needs

When the number of transfers reaches the value set in the DMA control register, the DMA control register generates an interrupt on the DMA channel interrupt vector.

If using DMA for reception, do not enable the RXNEIE bit

3. Error flags and interrupt generation in multi-buffered communications

In case of multi-buffer communication, if any error occurs during the transmission, the error flag will be set valid after the current byte.

RXNE and RXNE are used to set valid frame error, overflow error and noise error. They have independent error flag interrupt enable bits. If enabled, the initial phase

Any error will cause an interrupt after the current byte is transmitted.

Hardware flow control

The serial data flow between two devices can be controlled through the nCTS input and nRTS output

RTS and CTS flow control can be enabled by the RTSE and CTSE bits in the USART_CR3 register respectively.

1. RTS flow control

If RTS flow control is enabled, nRTS is valid as long as the USART receiver is ready to receive new data. When the receive register is empty, nTRS is valid.

Invalid, indicating that you want to stop transmission after sending the current frame.

2. CTS flow control If CTS flow control is enabled, the transmitter checks the nCTS input before sending the next frame. If nCTS is valid, the next data will be

If nCTS becomes invalid during transmission, the transmission will stop after the current transmission is completed.

When CTSE = 1, once the nCTS input is toggled, the CTSIF status bit is automatically set by hardware, indicating whether the receiver is ready for communication.

The CTSIE bit in the USART_CR3 register is set to 1 and an interrupt will be generated.