51 interrupt priority and interrupt nesting

The basic 80C51 series microcontrollers have 5 interrupt sources and 2 priority levels. Each interrupt source can be set as a high priority or low priority interrupt through software, which can achieve two-level interrupt service nesting.

Interrupt Priority

Before talking about interrupts, let me first define priority. If you understand what priority is, the following explanation will be easier to understand. Interrupt priorities are: query priority and execution priority.

Query Priority

The default query priority on the datasheet (IP register is not set, and is 00H after power-on reset):

External interrupt 0 > Timer/Event Counter 0 > External interrupt 1 > Timer/Event Counter 1 > Serial interrupt

First of all, the query priority cannot be changed or set. It refers to the order in which the interrupt arbitrator chooses which interrupt source to process first when multiple interrupt sources generate interrupt signals at the same time, and has nothing to do with whether the interrupt service program is nested. When the CPU queries each interrupt flag bit, it will query it in sequence according to the above 5 query priority orders. When several interrupts are requested at the same time, the interrupt flag bit with a high query priority will be queried first, but it does not mean that the interrupt with a high query priority can interrupt the interrupt service with a low query priority that has been and is being executed.

Execution priority.

The execution priority of the interrupt is the setting of the IP register. In the case of 2 priorities, if a bit is 1, the corresponding interrupt source is high priority; if it is 0, it is low priority.

Interruption Priority

1. When the CPU receives several interrupts at the same time, it responds to the interrupt request with the highest priority first. 
2. When several interrupt sources of the same priority request the CPU to interrupt at the same time, the CPU uses the internal hardware query logic circuit to determine which interrupt request to respond to first according to the query priority. 
3. The ongoing interrupt process cannot be interrupted by a new interrupt request of the same level or lower execution priority. 
4. The ongoing low execution priority interrupt service can be interrupted by a high execution priority interrupt request, unless the low priority interrupt service program being executed is set to prohibit the CPU from interrupting certain high priority interrupts.

For example: When the counter 0 interrupt and external interrupt 1 (according to the query priority, counter 0 interrupt > external interrupt 1) arrive at the same time, the interrupt service function of timer 0 will be entered; however, when the interrupt service function of external interrupt 1 is being served, no interrupt can interrupt it at this time, including the external interrupt 0 counter 0 interrupt which has a higher query priority than it.

For example, when there is more than one interrupt request in the same execution priority, there is an interrupt priority queuing problem. The interrupt priority queuing of the same execution priority is determined by the query priority determined by the interrupt system hardware.

For example: Set IP = 0x10, that is, set the serial port interrupt to the highest priority, then the serial port interrupt can interrupt any other interrupt service function to achieve nesting, and only the serial port interrupt can interrupt the service function of other interrupts. If the serial port interrupt is not triggered, the other interrupts still maintain the logical priority and cannot be nested with each other.

Interrupt Nesting

When an interrupt is being executed, if the interrupt priority register IP is set in advance, then when a higher priority interrupt arrives, interrupt nesting will occur. If it is not set, no nesting will occur. 
If an interrupt with the same priority is triggered, it is not "continuously applying", but its corresponding interrupt flag position, that is, a certain bit of the IE register, is set. After the CPU executes the current interrupt, it will re-query each interrupt flag bit according to the query priority and enter the corresponding interrupt. 
Remember that when IP is not set, the MCU will queue up for service according to the query priority. If you want to give priority to a certain interrupt, you need to set IP and change the execution priority (or physical priority). It should be noted that when IP is set, when a low execution priority interrupt is running, if a high execution priority interrupt occurs, it will nest the call to enter the high execution priority interrupt. 
If you are writing a program in C language and using a register group when servicing an interrupt, please note that two interrupt service programs with different execution priorities should not use the same group of registers.

Let's look at two questions as follows: 
1 When all interrupts are of low priority, if the overflow of timer 0 enters an interrupt. During this interrupt processing, external interrupt 0 is also triggered, so does interrupt nesting occur? 
2 If timer 0 interrupts and enters the interrupt handler, the trigger condition of external interrupt 1 is met at this time. Because timer 0 naturally has a higher priority than external interrupt 1, the interrupt handler of timer 0 continues to execute. Suppose during the execution of the timer interrupt handler, the trigger condition of external interrupt 1 disappears, then after the interrupt of timer 0 is processed, will the program still enter the external interrupt 1 handler?

Answer 1: When the priority of external interrupt 0 is set in advance by IP, the CPU will terminate the interrupt service of timer 0, enter the external interrupt 0 service program, and return to the timer 0 interrupt service program after execution. Otherwise, it will not. 
Answer 2: It will definitely enter the interruption; when the trigger condition of external interrupt 1 is met, the interrupt flag of external 1 will be set. Even if the trigger condition of external interrupt 1 disappears later, the set interrupt flag will not be cleared. Therefore, after the interrupt of timer 0 is processed, the program will still enter the external interrupt 1 processing program after judging that the interrupt flag of the external interrupt is 1. Only when the reti instruction is executed in the external interrupt 1 processing program will the hardware clear the interrupt flag of external interrupt 1 (this is why the interrupt return uses the reti instruction and cannot be replaced by ret)...

Interrupt Priority Register IP

×: Invalid bit. 
PS: Serial I/O interrupt priority control bit. PS = 1, high priority; PS = 0, low priority. 
PTl: Timer/Counter 1 interrupt priority control bit. PTl = 1, high priority; PTl = 0, low priority. 
PXl: External interrupt 1 interrupt priority control bit. Pxl = 1, high priority; PXl = 0, low priority. 
PT0: Timer/Counter o interrupt priority control bit. PT0 = 1, high priority; PTO = 0, low priority. 
Px0: External interrupt 0 interrupt priority control bit. Px0 = 1, high priority; Px0 = 0, low priority.