Systematic study of ARM Part 2 - ARM instruction set

1. Introduction:

definition:

    ARM instruction set: The set of commands that an ARM processor can run.

Features:

1. All ARM instructions are 32-bits long

2. Most are single cycle instructions 1T

3. All instructions can be executed conditionally

4. Use Load/Store architecture --- load/store instructions

          mov r1,100 @ r1 =*(100) Assign the contents of the cell with memory address 100 to r1. ARM instructions do not support this.

          mov r1,#100  @ r1=100

2. Data processing instructions:

1. Instructions:

•     Arithmetic instructions: ADD ADC SUB SBC RSB RSC

•     Logical instructions: AND ORR EOR BIC

•     Comparison instructions: CMP CMN TST TEQ

•     Data migration: MOV MVN

        Addition instruction ADD R1, R2, R3 R1 = R2 + R3

        Addition with carry ADC R1, R2, R3 R1 = R2 + R3 + C

        Subtraction instruction SUB R1, R2, R3 R1 = R2 - R3

        Reverse subtraction RSB R1, R2, R3 R1 = R3 - R2

        Subtraction with borrow SBC R1, R2, R3 R1 = R2 - R3 - !C

        Reverse subtraction with borrow SBC R1, R2, R3 R1 = R3 - R2 - !C

        Logical AND instruction AND R0, R0, #0X0F &

        Logical OR instruction ORR R0, R0, #0X0F |

        Logical XOR AND R0, R0, #0X0F ^

        Bit Clear BIC R0, R0, #9 R0 = R0 & (~#9)

        Comparison instruction CMP R1, #10 cpsr = R1 - 10

        Negative comparison instruction CMN R1, R2 cpsr = R1 + R2

        Bit test instruction TST R1, #3 cpsr = R1 & 3

        Test for equality TEQ R1, R2 cpsr = R1 ^ R2

        Data transfer MOV R1, R2 R1 = R2

        Data inversion transmission MVNR1, R2 R1 = R2

2. Condition code: the basis for determining whether an instruction is executed

•       EQ Equal

•       NE Not equal

•       GE is greater than or equal to

•       LE is less than or equal to

•       GT is greater than

•       LT is less than

3. How to execute the instruction:

1. There is no condition code following the instruction: Execute

2. The instruction is followed by condition codes:

  First, determine whether the condition code is established, CPSR condition bit and condition code flag

                Establishment -- Instruction execution

                Not true --- the instruction is not executed

         cmp r1, #3 @ r1- 3, the result affects the conditional bit of CPSR. The result is 0, Z=1. The result is not 0, Z=0.

       addeq r2, r1, r1 z=1, eq condition code is established; z=0, eq condition code is not established

4. Impact of conditional bits:

     1-- All instructions by default will not affect the conditional bit nzcv of the CPSR register

         In addition to the comparison instructions: Comparison instructions: CMP CMN TST TEQ

     1-- By adding S after the instruction, the execution of the instruction will definitely affect the nzcv bit

example:

    if (a==4 || a==10) --> cmp r4，#4

                   x=0;              cmpne r4,#10

                                        moveq r5,#0

4. Jump instruction:

        Branch : B{} label

        Branch with Link : BL{} subroutine_label

Relative jump:

        pc' = pc + offset

Jump range:

        ± 32 MB

5. Exchange Instructions:

(1) Instruction function: An atomic operation between a register and memory consisting of a memory read and a memory write.

            (Atomic operation means that it cannot be interrupted by other programs during the operation)

        One instruction completes the data exchange between memory unit and register

       swp (word swap): equivalent to

             temp   = *（Rn）

             *（Rn）= Rm

            Rd     = temp

                It is a 32-bit operation

       swpb (byte swap): Same as above, but operates on 8-bit data

            Swaps the lower 8 bits of a byte location in memory with that of a specified register.

(2) Semaphore Operation

(3) Note:

         This instruction cannot be implemented by writing a C language program

         Only hand-written assembly

6. Soft interrupt instructions:

(1) Instruction function: cause exception, system call

(2) Instruction format:

 SWI{}

7. PSR transmission instructions:

(1) Instruction function: The CPSR register does not allow data processing instructions to operate directly, but can only be operated by the PSR register.

(2) Instruction format:

      MRS{} Rd,cpsr                      @ Rd   = cpsr

      MSR{} ,Rm   @ cpsr = Rm

8. Coprocessor instructions:

Coprocessor register transfer instructions

   MRC: Move from coprocessor register to ARM register

   MCR: Move from ARM register to coprocessor register