Introduction to MCU Software Addressing Technology

　　In the data acquisition system with 80C31 as the control core, a large external RAM is often needed to store data. As we all know, 80C31 is an 8-bit CPU with a 16-bit address bus width. Its external RAM and ROM can directly address 64k bytes each (0000H-FFFFH). In the working process of 80C31, the addresses of ROM and external RAM are overlapped, but different control signals and instructions are used, while the extended I/O port and external RAM are uniformly addressed, occupying the address unit of the external RAM and using the same read/write control signals and read/write instructions of the external RAM.

　　In data acquisition systems, large-capacity external RAM is often required, and external devices such as displays, A/D converters, and printers must also be expanded with I/O. In the process of designing an intelligent sound level meter, the author requires that the 80C31 expand the external RAM to 64kB bytes, and the expansion I/O port uses the 82C55 chip to connect the character LCD, keyboard, A/D converter input, and printer. A software logic switch is used to achieve the overlapping use of the addresses of the 64k bytes of external RAM and the expansion I/O port, making full use of the data storage space directly addressed by the 80C31. The circuit is shown in the figure below.

 　　80C31 expands a program memory (EPROM) 27C64. The P0 port of 80C31 provides the low 8-bit address line through the address latch 74HC373, and the P2.0-P2.4 of 80C31 are the high 5-bit address lines, a total of 13 address lines (213=8k). Data reading is controlled by PSEN of 80C31, using MOVC instructions. Since only one EPROM is expanded, the chip select terminal CE of 27C64 is grounded.

　　80C31 expands 2 data memory chips 62256. 62256 is a 32kx8-bit static random access memory chip, made with CMOS technology and powered by a single power supply +5V. It has 15 address lines (215=32k), of which the lower 8 bits are provided by the P0 port of 80C31 through the address latch 74HC373. The P2.0-P2.6 address lines of the P2 port of 80C31 supply the higher 7 bits of address. The P2.7 line is connected to the chip select terminal CE1 of 62256 (1) and 62256 (2) without or through an inverter. When P2.7=0, 62256 (1) is selected and the address is 0000H-7FFFH. At this time, P2.7 is 0, and the chip select terminal CE1 of 62256 (2) is high through the inverter, and 62256 (2) is disabled. When P2.7=1, the chip select CE1 of 62256(1) is high, 62256(1) is disabled, and after inversion by 74HC04, the chip select CE1 of 62256(2) is low, 62256(2) is enabled, the address is 8000H-FFFFH, and the 80C31 expands the external RAM to 64k bytes (32KX2).

　　In order to meet the working requirements of the intelligent sound level meter, it is also necessary to expand the I/O port to connect the A/D conversion input, keyboard, display and printer. The author uses the 82C55 chip in the programmable parallel I/O port. Its A port is connected to the parallel output of the MC14433 dual-integral A/D conversion chip and programmed as input mode. Port B is connected to the printer and programmed as output mode. Port C is connected to the keyboard P6.0-P6.3 and programmed as input mode, as keyboard input line. P6.4-P6.7 is programmed as output mode and used as scan output line. The display uses DMC16230 character LCD, whose bus is connected to the 80C31P0 port data bus, the 82C55's port address selection terminals A0 and A1 (the registers of port A, port B, port C and control port can be selected respectively through programming A0 and A1) and the LCD's RS terminal (low level selects instruction register, high level selects data register) and R/W terminal (read and write selection) are respectively connected to the low address lines A0 and A1 of the address bus, the P1.0 line of 80C31, the A2 line of the address bus and the OE terminal (read control terminal) and WE terminal (write control terminal) of 62256, the chip select terminal CS of 8255 and the chip select terminal E of LCD are connected to the software logic switch.

　　The software logic switch is composed of logic elements and is controlled by software. Its working principle is as follows: when the program sets P1.0=1 of 80C31, an OR gate is connected to the chip select terminal CS of 82C55. When CS=1, 82C55 is disabled (low level selection). The signal of P1.0 port is connected to the chip select terminal E of LCD through two inverters and a NAND gate. When the chip select terminal E=0, LCD is also disabled (high level selection). The signal of P1.0=1 is low level through the inverter, and then connected to the OE and WE terminals of 62256 through two OR gates. In this way, the RD and WR signals of 80C31 can control the OE and WE terminals of 62256 respectively through two OR gates, and read and write operations are performed normally, so it is disabled when P1.0=1. 82C55, LCD only operates 62256, and when P1.0=0, the signal is high level through the inverter, and the OE and WE levels of 62256 are high level through two OR gates, thereby prohibiting the RD and WE terminals of 80C31 from reading and writing 62256 (low bit is valid). The selection of 82C55 or LCD by the signal of P1.0=0 depends on the level state of A2 in the address bus. When A2=1, the signal is low level through the inverter and the signal at P1.0, and then input to the CS terminal of 82C55 through the OR gate is low level, and 82C55 is selected. At this time, the signal of A2=1 and P1.0=0 is input to the E terminal of LCD through the inverter and the NAND gate at a low level, and LCD is prohibited. The port address of 82C55 is FFFCH-FFFFH. When A2=0, the signals of A2=0 and P1.0=0 are input to the CS terminal of 82C55 through the inverter and the OR gate as high level, and 82C55 is disabled. At this time, the signals of A2=0 and P1.0=0 are input to the E terminal of LCD through the inversion and the NAND gate as high level, and LCD is selected, and its address is FFF8H-FFFFBH. Through the above circuit analysis (the logical relationship is shown in Table 1), it can be clearly seen that the selection of P1.0 and address line A2 of 80C31 by software operation through the software logic switch effectively selects 62256, 82C55, or LCD respectively, realizes the overlapping use of addresses between them, and achieves the purpose of 80C31 expanding the direct addressing range of all external RAM.