Analysis of the application of CPLD devices in single chip controllers

    The objects of automatic control are varied and of various types, requiring the controller to be modular, standardized, and flexibly configured; in the era of commodity economy, the development cycle allowed for designers is getting shorter and shorter, from several years or months to several months or days; sometimes before the end of the contract, the user will ask for changes to the design terms. Therefore, designers need to develop controllers that are highly adaptable, easy to modify, and flexibly configured to meet user needs and win business opportunities.

    Considering the cost, it is sometimes a better choice to use a single-chip microcomputer as the core device and design a dedicated controller tailored to the controlled object.

    The combination of CPLD devices and single-chip microcomputers complements each other and brings out the best in each other

    Some advantages and disadvantages of microcontrollers

    The single-chip microcomputer has powerful information processing, logic analysis, decision-making and judgment capabilities. With the help of programs and through input/output interfaces, it can detect the state of the controlled object in real time, control its current or expected behavior, and form intelligent instruments and equipment.

    However, the microcontroller has insurmountable shortcomings and weaknesses, such as:

    Low-speed MCUs rely on executing instructions to complete various functions. No matter how high the working clock frequency is or how good the instruction timing is, its queued serial instruction execution method greatly reduces the working speed and efficiency. It is incapable of high-speed real-time simulation and high-speed data acquisition.

    Reset working mode: At the beginning of the microcontroller's operation, it takes some time to go through the reset process; when working, it will also reset under certain interfering mutation conditions. The complex reset process may be the root cause of unreliable operation.

    Program runaway Accidental factors can cause program runaway. Although there are "watchdog" or other anti-interference measures, in extremely complex situations, the microcontroller program may still runaway, thus entering a "freeze".

    In a single-chip microcomputer system, the chip of the single-chip microcomputer is connected to the logic circuit composed of other integrated circuits in the system through a printed circuit board. Once the design is changed, the board may be re-made, which prolongs the development cycle.

    Some advantages and disadvantages of CPLD devices

    With the rapid development of microelectronics technology, the scale of integrated circuits has become larger and larger, resulting in complex programmable logic devices CPLD and field programmable gate arrays FP2GA (the two devices have similarities, hereinafter referred to as CPLD devices). These devices contain a large number of programmable logic macro units or logic blocks, which can be arbitrarily combined to design logic circuits with different functions.

    The clamping level of the input pin and the original level of the output pin of the CPLD device can be preset, and the preset level can be reached immediately after the device is turned on, and the status is clear. The input signal of each logic macro unit or logic block only takes a few ns to tens of ns to be reflected at the output end, and the signal transmission efficiency is very high, which is suitable for high-speed sampling and other occasions.

    The interconnections between programmable logic macrocells or logic blocks are in the same package, which is less affected by external interference and has good electromagnetic compatibility (EMC) performance. However, for designers, the biggest advantage of CPLD devices is that they can be programmed on site. When changing the logical relationship, there is no need to change the external circuit board. You only need to use a graphical language program or a hardware description language program to change the circuit, generate download editing software, and input the CPLD device through a download cable. It is very convenient and especially conducive to the trial production of new products, greatly shortening the development cycle.

    Although CPLD devices can be used to form various logic circuits at will, they are not as "intelligent" as microcontrollers in terms of information processing, logic analysis, decision-making, etc. Although CPLD devices can be used to simulate microcontrollers, there is still a gap. They are generally used as "state machines" or auxiliary logic circuits.

    The combination of CPLD devices and single-chip microcomputers can complement each other's advantages

    If the two are combined, the controller can complement each other. A large number of industrial control objects are not high-speed adjustment systems. In this case, the control circuit in Figure 1 saves hardware costs, is suitable for the characteristics of CPLD devices, is easy to debug, and has strong anti-interference ability.

    Figure 1 Block diagram of a controller based on a single-chip microcomputer and CPLD devices

    If it is a high-speed regulation system, a parallel A/D conversion integrated circuit should be used as the sampling and conversion circuit of the input signal VI.

    Switch type interface

    The switch-type input/output terminals of the CPLD device and the external device can be connected as shown in Figure 2 to form a switch-type interface similar to that of a PLC programmable controller. Some designers insert a shaping circuit at point a. In fact, when the CPLD device is combined with a single-chip microcomputer, the influence of jitter can be eliminated with the help of filtering software, making the circuit simple. After actual use, the effect is very good.

       Figure 2 Switch type input/output interface

    CPLD devices are more advantageous than single-chip microcomputers in situations where high-speed sampling or the competition phenomenon of pulse signals is used. For example, a certain type of sectional warping machine has a yarn cage diameter of 650 to 1000 mm and needs to distinguish the direction of rotation. When the yarn cage is running at high speed, the minimum time difference between the A and B signals is about 240ns. Such a time difference is difficult for a single-chip microcomputer to handle; sometimes the operator needs to rotate the yarn cage to adjust the position, the speed is often almost zero, and the direction may be changed repeatedly.

    CPLD devices are used to form a direction determination circuit as shown in Figure 4. The A-way signal is input from the IN05 pin, the B-way signal is input from the IN10 pin, and the direction signal is taken from the DATA0 of the data bus (waveform shown in Figure 5) and transmitted to the single-chip microcomputer for detection and pulse counting.

    The difficulty of this application lies not only in determining the direction at high speed, but also in the complex and changeable situation when the worker rotates the sarong. Although the sensor is equipped with a Schmidt shaping circuit, when the sarong passes through the sensor at a low speed, the time to cross the threshold level is prolonged, which will produce a series of unstable jumps and cause counting errors.

    Figure 3 Schematic diagram of sarong sensor signal and waveform

    Figure 4 Direction determination circuit

    With the help of the special processing program of the microcontroller and other logic circuits in the CPLD device, the controller of the warping machine project can reliably detect the direction and number of pulses regardless of high or low speed, and no errors have occurred.

    Figure 5 Simulation waveform of the direction determination circuit

    Analog signal interface

    Analog signal input interface

    When the control object does not require high-speed sampling and high-speed adjustment, the analog-to-digital conversion form shown in the controller block diagram of Figure 1 can give full play to the advantages of the programmable logic macro unit of the CPLD device. The V/F converter converts the input voltage signal into a frequency signal for the counter (not shown in Figure 1) in the CPLD device to count, thereby converting the analog quantity into a digital quantity. The word length, base, and mode of the counter can be arbitrarily programmed as needed, which is more flexible and convenient than using the counter in the microcontroller. It is not described in detail here.

    When the control object is a high-speed system, a parallel A/D conversion integrated circuit can be used. In this case, parallel port control is appropriate, and the A/D circuit can be controlled in the conventional way through a single-chip microcomputer or CPLD device.

    Analog signal output interface

    The output regulation signal can be converted into digital-to-analog format by using a pulse width modulation (PWM) waveform plus a low-pass filter. The higher the PWM frequency, the better the filtering effect. The digital-to-analog conversion channel is shown in Figure 6.

    Figure 7 is an example of an 8-bit counter PWM waveform generator designed in a CPLD device. By filling in different count initial values, pulse trains with different duty cycles will be output at the PWMOUT terminal (see Figure 8).

    Figure 6 Schematic diagram of digital-to-analog conversion channel

    Figure 7 8-bit counter PWM waveform generator example

    Figure 8 Pulse width modulation waveform comparison

    In Figure 7, the clock pulse is input from the P32 pin, WRN is the write enable signal input terminal, and PWMOUT is the output terminal.

    If only CPLD devices are used, the circuit for forming the period and pulse width of the PWM wave will be more complicated. After combining with the single-chip microcomputer, the period of the PWM waveform is the period of the WRN signal of the single-chip microcomputer periodically accessing the counter, and the pulse width is determined by the initial count value filled in by the single-chip microcomputer through the data bus (DATA0~7). The consumption of the number of programmable logic macro units or logic blocks in the CPLD device is reduced. In Figure 6, the shaping circuit mainly plays the role of limiting and isolating. After limiting, the amplitude is kept consistent, and the steepness of the rising and falling edges of the pulse is increased to ensure that the voltage amplitude of the subsequent conversion mainly depends on the pulse width, reducing additional errors.

    The filter circuit affects the linearity of the conversion. According to different project requirements, passive filters, active first-order and second-order low-pass filters can be used. Butterworth filters have flat passband amplitude-frequency characteristics and are most suitable for the needs of this conversion circuit. Taking the Butterworth second-order low-pass filter shown in Figure 9 as an example, its cut-off frequency fo is:

    Figure 9 Second-order low-pass filter

    The cut-off frequency fo should be greater than the signal bandwidth edge, but much smaller than the frequency of the PWM signal. The values ​​of the filter R and C directly affect the converted ripple amplitude and conversion rate. The requirements of the two for R and C are opposite, and they should be considered in a balanced way. If necessary, select the appropriate value through experiments.

    The accuracy of the circuit that realizes digital-to-analog conversion by adding low-pass filtering to the pulse width modulation (PWM) wave mainly depends on the word length of the counter, the frequency of the PWM, the form of the low-pass filter and the selection of components. Paying attention to these points, the conversion effect is satisfactory. This article takes an 8-bit counter as an example. In actual applications, considering various factors, 10-14-bit counters are generally used.

    The power amplifier stage in Figure 6 is mainly used to convert the output signal of the filter into voltage and current signals that meet the requirements of Type II and Type III instruments in the form of appropriate amplification and feedback, or convert it into other trigger control signals so as to connect with the controlled object and adjust its working state.

    Conclusion

    The physical mechanism of CPLD devices is pure hardware circuit like 74 series and CD4000 series integrated circuits, which are very reliable. The complicated development work is realized by powerful EDA software, which has a low entry threshold and is easy for beginners to use. At present, it is favored by more and more designers, and it is only a matter of time before it is popularized.

    With the development of microelectronics technology, I believe that CPLD devices will make great progress and may be increasingly closely integrated with microcomputers, so that the boundary between the two is blurred, and you are in me and I am in you.

    When developing products, the organic combination of CPLD devices and single-chip microcomputers not only shortens the development cycle, but also makes the controller flexible in configuration, easy to modify, and highly adaptable, increasing the freedom of development. It is easy to meet the diverse needs of users and thus win business opportunities.