Design of electronic bell ringer based on IIC clock

　　When Mcs-51 microcontrollers were already widely used, there was no I2C protocol standard. But today, I2C has been widely adopted as a standard data exchange protocol between ICs. Mcs-51 microcontrollers without I2C interfaces often exchange data with standard I2C devices, so articles about Mcs-51 emulating I2C interfaces are often seen in newspapers.

　　Recently, in order to design an electronic bell based on I2C clock, I first conducted a practical programming of MCS-51 simulating I2C interface operation. I thought that I could easily complete it with all the information at hand, but I didn't expect it to take a lot of trouble, so I would like to make a summary of my experience.

　　1. Hardware structure of FG device

　　The I2C bus consists of two signal lines, SDA and SCL, where SDA is the data line and SCL is the clock signal line. The I2C bus can be connected to chips with standard I2C interfaces, such as SRAM, E2PROM, ADC/DAC, RTc, I/O port, DTMF, clock chip, temperature chip, etc., to form a complete digital processing system. When powered on, both SDA and SCL are pulled to a high level state by the pull-up resistors connected to their respective lines.

　　As can be seen from the figure above, each I2c device has four signal ports: sDA out, sDA in, scL out, and SCL in. When the scL output of a device connected to the same I2c bus is low, the SCL bus will be pulled low by it. The same is true for the SDA bus.

　　However, the sDA and scL signal ports are controllable inside the device.

　　When the host starts the I2C bus and sends the device address to the I2C bus, each device will receive the SDA input and SCL input signals, but only the I2C device whose device address is consistent with the received device address information will continue to receive subsequent information. Other devices will close their input ports until the next time the host starts the I2C bus.

　　2. I2C transmission protocol standard

　　The I2C bus is an asynchronous serial communication bus. The host can start the I2C bus at any time and send the device address to establish communication with the corresponding slave device. At each moment, only one host and one slave device can occupy the I2C bus. The I2C transmission protocol allows the bus to access the same I2C bus. In the multi-host I2C bus system, the only host at a certain moment is determined through the coordinated management of multi-master competition, and the other hosts are placed in the slave position waiting for the host to decide. This article only involves the data exchange between the MCS-5l microcontroller and the I2C slave device, so it only simulates the process of a single host operating the I2C slave device.

　　(1) Device address and internal address of IIC device

　　Each slave device connected to the I2C bus must have a unique device address, which is the first eight-bit binary data sent by the host after starting the I2C bus. This eight-bit binary number consists of three parts: four bits of inherent address code (D7-D4), three bits of pin address code (D3-D1) and one read/write select bit (1/0, Do).

　　The four-bit inherent address code is a fixed code that has been solidified in the chip before the I2C device leaves the factory and cannot be changed. For example, the device address of the E2PROM chip 24CXX (including compatible chips produced by various companies) is 1010, the device address of the LED driver sAAl064 is 0111, and the device address of the clock chip PcF8563 is 1010. The three-bit pin address code can be formed according to the device chip pins A2, A1, AO connected to the power supply or ground (I/0) to determine the individual slave device chip on the same bus. There are A2, A1, and A0 pins on the 24CXX chip, but because some chips occupy the address coding resources internally, the A2, A1, and A0 pins of some chips are not all useful, but empty pins. Therefore, the number of chips that can be connected to a bus is also different. 24C02 can connect 8 chips. The pins A2, A1, and A0 of each 24C02 are set to 000-111 respectively. Then the host can access different 24C02 chips by sending different device addresses. 24C16 can be regarded as 8 24C02 chips as one. The host can access different blocks inside 24c16 by sending different device addresses.

　　Chips above 24C32 have internal address codes divided into two bytes, breaking through the limitation of 11 bits of address coding resources (3 bits of device address + 8 bits of internal address), so the bus capacity is also expanded.

　　There is a certain amount of data storage unit inside the device chip, which is determined by the internal address code (also called sub-address). The internal address code of the general I2C device is an eight-bit binary data (A7~AO), which can address 256 bytes. If it is not enough, two bytes are needed to represent it: high byte (A15~A8) and low byte (A7-AO). If it is still not enough, it can be expanded. It can be seen that the I2C protocol has a strong vitality.

　　(2) Built-in address counter

　　In order to facilitate the read and write operations of the internal data storage unit of the IIC device, an address counter is built into the 24Cxx chip. After reading and writing a byte, the address counter automatically increases by 1. In this way, after the first byte is read and written, the address counter has already pointed to the next storage unit when reading and writing for the second time. When reading data, the starting unit address is sent first, and then any bytes can be read continuously until the address counter reaches the maximum value and flips to 0, and the next round of counting is performed. For example, 24C16 (internal address encoding range 000H~7FFH) first sends the starting unit address 005H, and then reads 7FFH bytes continuously. The first 7FAH bytes are the unit contents of 005H~7FFH, and the last 5 bytes are the unit contents of 000H~004H.

　　However, when writing data, the address counter is limited to the lower three (or four, five, six) bits. Take 24C01 as an example. When it counts to 1000B, there is actually no carry, but it returns to 000B to start the next round of counting. Therefore, if it is a single-byte write, the reliable way is to send the address code of the unit to be written before sending the write data. If it is to write to consecutive units (also called page write), send the starting unit address first, and then send the n bytes to be written. The number of bytes that can be written continuously at each time for 24COI/02/04/08/16/32/64/128/256 is 8/16/16/16/16/32/32/64/64 respectively. But this is the continuous number when the starting unit address is 0. If the starting unit address is not 0, the actual storage location of these bytes is not continuous. For example, 24C16 (internal address code range 000H～7FFH) first sends the starting unit address 005H, and then writes 16 bytes continuously, then the first 11 bytes are written into the 005H～OOFH units, and the last 5 bytes are written into the 000H～004H units. If 17 bytes are written continuously, the first byte content stored in the 005H unit is overwritten by the last 17th byte, resulting in the loss of the first byte content.

　　This is where the page writing method makes it more difficult to understand.

　　(3) General process of reading and writing IIC devices

　　Before reading or writing I2C devices each time, the host must first start the I2C bus, as shown in Figure 2. When the clock line scL is at a high level, the data line sDA changes from a high level to a low level, which starts the I2C bus. This process is generally called the start signal s. Next, the host will send the first eight bits of binary data to the I2C bus - the device address (including the last "read-write select bit"). If the visited I2C device confirms that it has been selected, it will pull SDA to a low level when the host sends the ninth scL clock signal, forming an acknowledgement signal AcK. At this time, the host sets sDA to a high level and waits for the acknowledgement signal sent back by the visited I:c device. After receiving the acknowledgement signal, the host starts to perform the corresponding read and write operations.

　　After a read or write is completed, the host sends a termination signal P, and all I2C devices will restore sDA and scL to their initial high state, as shown in the figure below. When the clock line SCIJ is high, the level change of the data line sDA from low to high stops the I2C bus data transmission.

　　According to the difference of the last "read-write select bit" of the device address, it can be divided into two situations: read and write. However, as mentioned above, there are still differences in the operation of read and write. The following describes the four situations of byte read, sequential read, byte write, and page write respectively.

　　After the host sends each byte, it sets SDA to a high level and waits for the response signal sent back by the visited I2C device. This is omitted in the following process, but it is indispensable in the actual process, so it is specially explained. Similarly, after the host receives 1 byte of data sent by the IIC device, it will also send a signal to the I2C device, that is, pull SDA to a low level (equivalent to the ninth bit being 0) at the 9th scL clock, as shown in the figure below.

　　1 byte of data is sent → a termination signal P is issued.

　　If the sub-address is not sent before reading, the next byte pointed to after the last read or write is read. This also applies to the sequential read process. It should be noted that the last bit of the device address sent before the sub-address should be 0, which is a write operation, which is prone to errors.

　　Sequential reading first sends the sub-address of the unit to be read: send a start signal s → send the device address (the last bit is 0, write operation) → send the sub-address → send a stop signal P; then send a read command: send a start signal s → send the device address (the last bit is 1, read operation) → receive 1 byte of data sent by the I2C device → send an acknowledgement signal ACK → repeat receiving and acknowledging signals until the bytes to be read are read → send a stop signal P.

　　After reading the bytes to be read, sDA can be set to a high level (equivalent to the ninth bit being 1, called the anti-state response bit) when reading the ninth SCL clock of the last byte, which is equivalent to clearly informing the I2C device that the reading has ended.

　　When writing a byte, first send the sub-address and then send the data to be written: send the start signal s → send the device address (the last bit is 0, write operation) → send the sub-address → send the data to be written → send the end signal P.

　　When writing a page, first send the starting sub-address and then continuously send the data to be written: send the start signal S → send the device address (the last bit is 0, write operation) → send the starting sub-address → send the first data to be written → repeat until all the bytes to be written continuously are sent (different devices have different restrictions on the number of bytes that can be written continuously) → send the termination signal P.

　　When the number of bytes to be written exceeds the number of bytes that can be written continuously by the device, the page write process should be called cyclically to write the bytes to be written continuously in batches.

　　3. MCS-51 simulates I2C interface

　　After understanding the I2C transmission protocol standard, we can use the two port lines of the Mcs-51 microcontroller to connect to the SDA and SCL pins of the I2C device, and use software to simulate the I2C transmission protocol to read and write the I2C device. It should be noted that the I2C device can only be regarded as a relatively fast device in the Mcs-51 system. The standard transmission rate is no more than 100kbps, and the SCL low level period should be maintained for more than 4.7μs, and the high level period should be maintained for more than 4.0μs. Therefore, a delay subroutine should be added to the program to meet the response speed of the I2C device.

　　In order to make it easier for readers to develop and use I2C, the standard complete program for Mcs-5l to simulate I2C interface is provided on the website of this magazine (W3NW.eleworld.eom), and a matching vB program is written. By connecting to the MCS-5l serial port via the RS232 serial port, any I2C device can be easily read and written on the computer.

　　Take the connection between 89C2051 and 24Cxx as an example, as shown in the figure above, P1.7 is the scL line, P1.6 is the sDA line. The serial port of 89C2051 is connected to the computer RS232 serial port through MAX232. After compiling the I2C 51.asm file that simulates the I2C interface, burn the program memory of the Mcs-51 microcontroller , and you can read and write the connected I2C device on the computer.

　　The following is an introduction to the use of the vB program. Open the I2C reader.EXE, and the main interface is as shown above. First, set the serial port number, baud rate, and data bit number. The default byte read first sends the sub-address of the unit to be read: send the start signal s → send the device address (the last bit is 0, write operation) → send the sub-address → send the end signal P; then send the read command: send the start signal S → send the device address (the last bit is 1, read operation) → the receiving I2C device is set to "COMl: 4800, n, 8, 1".

　　Click the "Set Serial Port Number, Baud Rate, Data Bits" button, and a dialog box as shown above will appear. After the settings are completed, you can click the "Test" button to test the serial line communication. If the connection and settings are correct, the "Communication is normal!" prompt will appear in the test information box. If the connection is tested to be correct, you can read and write I2C devices.

　　Select the I2C device to be read. If the device is not in the list box, you can also click the "Add Device" button to add it by yourself. Click the "Read" button, and the "Enter Read Range" dialog box as shown above will appear. Enter the start address and end address of the unit block to be read, click "OK", and the data content of the corresponding unit block will be displayed in the text box of the main window. The start address and end address can be expressed in hexadecimal and decimal. If you use any system to enter, the program will automatically convert it for user convenience.

　　Similarly, enter hexadecimal data such as "01 F5 7D" in the text box of the main form, and click the "Write" button to write the data into the specified unit of the I2C device. The difference is that the end address when writing is automatically generated by the start address and the number of written data, and the user only needs to enter the start address. The written data will be divided into small blocks of less than eight bytes and sent to the 51 microcontroller serial port in batches with a delay to ensure that it is correctly written into the I2C device.

　　Click the "Save" button to save the data displayed in the text box as Hex or Bin file format.

　　Click the "Send File" button to write the data content in Hex or Bin file format to the specified unit block of the I2C device.

　　4 Conclusion

　　This article analyzes the hardware structure and interface protocol of I2C devices in detail, and based on this, gives a program example of simulating I2C operation with Mcs-51 microcontroller without Izc interface. At the same time, it also provides a solution for reading and writing I2C devices on a computer, hoping to provide some help and inspiration to readers who want to use I2C devices for development.