DVI interface application system based on TFP401A

    At present, analog interfaces have become the standard for desktop monitors, but the popularity of PFD displays requires a completely digital interface. This is because analog interfaces are completely unnecessary for flat-panel displays, while digital interfaces do not have to adjust clocks and phases, and have the advantage of lossless signal transmission. With the promotion of digital flat-panel displays, the need for digital graphic connections has become clear. The DVI digital video interface standard proposed by the Digital Display Working Group (DDWG) solves the above problems very well, and is also compatible with traditional VGA interfaces and DVI interfaces. It is currently a very promising PC video interface standard.

    1 DVI interface system

    DVI is mainly based on TMDS (Transition Minimized Differential Signaling) technology to transmit digital signals. TMDS uses advanced coding algorithms to convert 8-bit data (each primary color signal in R, G, B) into 10-bit data (including line field synchronization information, clock information, data DE, error correction, etc.) through minimum conversion, and uses differential signals to transmit data after DC balancing. It has better electromagnetic compatibility than LVDS and TTL, and can achieve long-distance, high-quality digital signal transmission with low-cost dedicated cables. The connection transmission structure of TMDS technology is shown in Figure 1.

    DVI digital signal transmission has two modes: single link and dual link. When single link is used, only channels 1, 2, and 3 shown in Figure 1 are used for transmission, and the transmission rate can reach 4.9 Gbps, while dual link can reach 9.9 Gbps.

    2 Application of DVI interface

    The general structure diagram of the DVI application system is shown in Figure 2. The DVI interface is the DVI output of the graphics card; TFP401A is the receiving chip of the TMDS signal and is the core of the entire receiving system; AT2402 is the I2C serial bus memory of ATMEL Company , which is used to store EDID data.

    The TMDS link transmitter of the DVI interface is generally directly integrated by the display control chip. Display adapters with DVI functions have been integrated into the TDMS transmitter, and the performance can generally meet the DVI1.0 specification; graphics cards with ATI's display control chip as the core are generally responsible for TDMS signal transmission by the onboard SILICon Image's Si1164 chip. The TDMS receiver and signal decoding of the DVI interface are the most important in the application. This article introduces the TDMS receiving system with TFP401A as the core.

    2.1 Functional structure of TFP401A receiver

    TFP401A is a TDMS signal receiving chip in TI's PanelBus flat panel display product series. It adopts advanced 0.18μm EPIC-5TMCMOS process technology, uses 1.8 V core voltage and 3.3VI/O voltage, has low noise and low power consumption characteristics, and its PowerPADTM packaging technology can ensure the thermal stability of the chip. It is mainly used for LCD desktop displays, and can also be used in other high-speed digital video applications.

    The main functions of TFP401A are as follows:

    ◇Supports SXGA (1280 X 1024, 80 Hz) pixels, with a clock speed up to 112 MHz;

    ◇Support 24-bit (224=16.7 M) true color (1pixel/clock or 2pixel/clock);

    ◇The terminal impedance matching resistor is made by laser precision technology;

    ◇Using 4x oversampling technology; jitter suppression can reach 1 pixel/clock;

    ◇It has the function of suppressing jitter of horizontal synchronization signal.

    The specific pin signals of TFP401A can be found in the data sheet. Its internal structure and functions are shown in Figure 3, where the input RX(2~0)+- and RXC+- are 4-channel TMDS signals from the host after serial-to-parallel conversion encoding, and its output signals mainly include odd and even pixel signals (QE[0:23], QO[0:23]), pixel clock ODCK, pixel valid DE, line/field synchronization (HSYN/VSYN) and synchronization detection SCDT, etc.

    TFP401A determines the activation status of the link by detecting the state change of the DE signal. After 106 pixel clocks, if the DE state does not change, the link is considered to be inactive, and the system outputs SCDT = 0. In the case of SCDT = 0, if it is found that the DE signal has two transitions within 1024 pixel clocks, the link is considered to be activated, and SCDT = 1. The synchronous detection indication signal terminal (SCDT) of the device can be directly connected to its output driver power control terminal (PDO), so that the chip can automatically manage the power supply of the output driver according to the activation status of the TMDS link. The PD terminal provided by TFP401A can be used to control the power supply of the entire chip. This terminal is a system-level power management control terminal. It is generally not recommended to connect directly to the chip SCDT terminal during design.

    2.2 TFP401A output control signal connection

    The output control signal terminals CTL1, CTL2, CTL3, VSYNC, HSYNC, and DE of TFP401A should generally be driven by Schmitt triggers to ensure that the low voltage differential signal can be well transmitted to the next level device. SN74LV14A can be used to complete this function during design. The output address data signal must have a strong enough driving capability, which requires driving before being transmitted to the signal processing circuit. The wooden design increases the driving capability through the buffer driver chip 74F244.

    2.3 Power supply and decoupling of TFP401A chip

    The system based on TFP401A is mainly divided into four circuits: analog comparator, phase-locked loop (PLL), digital circuit and output signal driver. Among them, the VCO (voltage-controlled oscillator) inside the PLL loop is most sensitive to power supply fluctuations. Because it provides a reference clock for the circuit, the PLL has the highest power supply requirements; followed by the analog comparator; the digital circuit has relatively low power supply requirements, but consumes the most power. In the TFP401A application guide provided by TI, the power supply adopts a unified power supply, and the 4-way power supply uses 4 inductors for isolation, but this will increase the volume and weight of the circuit, and the presence of inductors will also cause interference to the analog circuit. Therefore, in the case of no need to strictly control costs, it is recommended to adopt the power supply method shown in Figure 4, that is, use 2 TPS7333Q to power the analog and digital circuits respectively. TPS7333Q is a low-dropout linear voltage regulator circuit with high power supply noise suppression capability, which can provide a 3.3 V power supply voltage for the chip. AVDD and PVDD are the comparator power supply and PLL power supply of the analog circuit respectively; OVDD and DVDD are the output drive power supply and digital power supply of the digital circuit respectively. By providing separate power supplies for analog and digital circuits, and adding a smaller inductor in series to circuits with higher power requirements to further smooth the power ripple, the circuit size can be greatly reduced and the power supply quality can be improved.

    2.4 Heat dissipation and copper plating of TFP401A

    PowerPADTM packaging technology makes TFP401A have high working thermal stability. There is a heat dissipation pad of about 25 mm at the bottom of the chip. It is recommended to connect it to the signal ground of the PCB board when soldering the chip, which can provide better EMI performance and improve the suppression ability of line surge current on power supply noise. In specific operation, a through-hole pad with a diameter of about 100 mm can be placed at the position of the chip heat dissipation pad, and the inside can be filled with solder and connected to the ground copper of the bottom layer, so that the heat generated by the chip can be transferred to the back through the solder filled in the through-hole and radiated out.

    Since TFP401A usually works in a high-frequency digital-analog mixed signal environment, it is recommended to apply copper to the top and bottom layers of the PCB board. Large-area ground copper can provide a relatively quiet working environment for the chip on the one hand, and it is also beneficial to the heat dissipation of the chip on the other hand. Although TFP401A provides 4 types of power pins and ground pins such as analog and digital on the chip, it is actually difficult to separate the 4 ground wires and ground them at one point. Generally, all ground pins are connected to the ground copper, and vias are used to divert the current on the ground copper, so that most of the ground current of the 4 types of ground wires flows along different paths and finally converges to one place.

    2.5 Signal routing and impedance matching

    In the DVI link structure, at the XGA 60Hz field frequency, the link clock can reach 650 MHz, and the sampling clock inside the chip will reach 615 GHz. At such a high operating frequency, the chip will become very sensitive to the circuit wiring method and the pad size. Roughly estimated, there is about 1 nH inductance on a 1 mm wire in a high-frequency circuit. In this way, at a link frequency of 650 MHz, a 10 mm wire will produce an impedance of 40Ω. Therefore, the signal input pins of the chip should be as close to the DVI interface socket as possible. Signal lines of different signal channels should avoid parallel routing, and a ground line should be used as much as possible to isolate the signal lines to avoid crosstalk between high-frequency signals as much as possible.

    At the signal output end of the chip, the clock output pin (ODCK) can output a square wave signal of up to 86 MHz, and the pixel data output pin often operates at a frequency higher than 25 MHz. If the lead from the pixel data to the display control circuit is long, the impedance matching of the output signal must be considered. Due to the reflection, overshoot, undershoot of the signal and the influence of the surrounding environment, if matching is not performed, it is easy to cause logical confusion in the control circuit of the display data receiving end. Therefore, in practical applications, it is necessary to try to connect matching resistors in series near each signal output end of TFP401A to suppress the secondary reflection of the signal. The resistance value can generally be selected between 33 and 100Ω. The author selected a 33Ω matching resistor when designing, and the corresponding signal connection width is 20 mil.

    3. Brief Analysis of VESA Standards

    Currently, dual-display graphics cards on the market usually use the 15-pin VGA interface as the main display interface of the system, and the DVI interface as the auxiliary display interface. When the DVI interface is not connected to a monitor, the display signal of the auxiliary channel is turned off. In order to correctly start and use the DVI interface signal, it is usually necessary to master several important VESA display standards.

    3.1 DDC interface design

    DDC (DisplayDataChannel) is the display data channel. DDC2B is used in the DVI protocol, which is a communication standard based on the I2C bus protocol. The host and the display device query and transmit EDID data through the DDC channel to achieve the correct use and plug-and-play of the display device. The main DDC standards are as follows:

    DDC1: The original DDC standard is a one-way data channel that continuously transmits EDID information from the display to the host.

    DDC2: A bidirectional data exchange channel that allows the host to read the display's extended display information EDID.

    DDC2B: Allows bidirectional code exchange between the host and the display. The host can send display control commands to the display.

    DDC2B+: A bidirectional data transmission channel that allows the host to control the display. This standard has a wider communication bandwidth and can even connect other peripherals such as joysticks and mice .

    The core circuit for implementing the DDC interface is the EEPROM circuit of the serial I2C bus. The key to circuit design is to meet the requirements of the I2C bus standard. In order to ensure circuit safety during design, a 50-100Ω current limiting resistor must be connected in series.

    3.2 EDID Standard

    Implementing the DDC interface generally requires writing EDID data. E-DID is a data structure with many different variables. It defines the display identification and various display capabilities to the host and is independent of the data transmission protocol between the display and the host. The key to writing EDID is to clearly understand the EDID data format and extended display identification data, which contains the manufacturer of the display device, product serial number, EDID version information, etc., and also indicates the display capabilities supported by the display device, including display resolution, field frequency, line frequency range, blanking signal timing structure, display chromaticity coefficient and other parameters. These parameters are stored in a dedicated 1 Kb EEROM memory in the display (that is, the E-DID data structure is 128 Byte). The PC host and the display access the data in the memory through the DDC data line to determine the display properties of the display (such as resolution, aspect ratio, etc.) and other information.

    3.3 HPD (HotPlugDetectionl Hot plug detection

    HPD is used to monitor the connection or removal of display devices. When the system detects that a display device is connected through HPD, it will access its EDID data through the DDC channel in order to correctly drive the newly connected display device.

    The DVI interface protocol requires that DVI interface compatible display devices must be able to provide EDID1.2 or EDID2.0 data. When the system starts or when the user modifies the display properties of the monitor, the EDID data should be queried through the DDC channel. If the connected device has an error or the EDID data is not detected, the system will not start the signal output of the DVI interface. In actual application, the EDID data should be written into an EEPROM of the I2C bus interface. The clock line (SCL), data line (SDA) and pins 6 and 7 of the DVI interface socket can be connected. Connecting the 16th pin of the DVI interface socket to the 14th pin (DVI interface DDC +5V power supply terminal) through a 1 kΩ pull-up resistor can form the HPD signal of the display device.

    4 Conclusion

    This article analyzes the architecture and basic principles of DVI from the perspective of engineering application, and also introduces in detail an application design method of a DVI receiving system that has been experimentally verified. The purpose is to enable readers to quickly master the DVI communication protocol and the design of its application circuits, so as to extract video information from the interface and get rid of the research on the complex hardware principles inside the computer, so that the high-quality digital video information of the DVI interface can be developed and utilized according to user requirements.