Design of real-time digital video storage system for CCD cameras based on FAS466

Since the image data volume of high-frame-rate, large-array CCD digital cameras is very huge, the storage flow exceeds 50MBps. In addition, the image output rate is also relatively high, so the real-time recording of high-speed image data is a difficult problem to solve. The general solution for digital video storage of high-frame-rate, large-array CCD cameras is based on high-performance computer architecture, combining the PCI bus video acquisition card with a high-performance IDE hard disk system or a SCSI storage hard disk system based on a PCI-SCSI bridge to complete the task. This solution is relatively easy to implement, but there is a bus bottleneck problem. One storage occupies two PCI buses, and it is also limited by the operating system and file system. Therefore, in practical applications, the storage speed is difficult to exceed 40MBps. In response to this problem, this paper designs an image data storage method that is separated from the computer platform, uses FPGA chips to control the timing, and uses VHDL language programming to implement the microprocessor and DMA control functions, thereby coordinating the SCSI protocol processor to realize data transmission. The use of FPGA reduces the size of the circuit board, reduces the cost, and increases the storage rate compared to using a DMA controller alone.

1 System hardware structure design

To implement SCSI protocol and hard disk storage, hardware support such as microprocessors, DMA controllers, SCSI protocol controllers, data buffers, and corresponding software control modules are usually required. This system. DMA control is realized by programming FPGA. The structure diagram of the image data storage system is shown in Figure 1.



1.1 Microprocessor

The microprocessor is responsible for coordinating and controlling each module. The dedicated high-speed hard disk storage device designed in this system realizes continuous high-speed data storage, which requires high data processing speed, so a DSP microprocessor is used. The main functions of the microprocessor are as follows:

    (1) Complete the start and end control of external data transmission.
    (2) Reset and start operation of FPGA.
    (3) Initialize the FAS466 and interrupt the abnormal transmission.
    (4) Read and write control of the internal registers of the protocol control chip, thereby controlling the command transmission and status monitoring of the SCSI bus. Interpret, execute and manage SCSI command information; translate, execute and manage the information status from the SCSI bus.

1.2 DMA controller The DMA controller controls the data transmission between the data buffer

of the data sending or receiving source and the internal buffer of the SCSI protocol controller, so as to control the data transmission between the data source and the SCSI bus by coordinating with the DMA interface of the protocol controller. This design uses FPGA devices and uses VHDL language programming to implement the DMA controller function. Instead of using a dedicated DMA controller, the following factors are considered: the data transmission rate of this design reaches 50MBps, which is difficult for a general dedicated DMA controller to handle; the connection between the dedicated DMA controller and the SCSI protocol control chip requires a large number of logic conversion circuits and peripheral connections, which increases the difficulty of design; using FPGA devices, in addition to completing the DMA control function, you can also design modules such as logic conversion and system reset in the circuit, which reduces the size of the device and facilitates future upgrades and improvements to the system. 1.3 SCSI protocol processor (FAS466) The SCSI protocol processor is the execution component of the SCSI bus operation. Each company has a dedicated SCSI integrated circuit chip as a protocol controller, such as Qlog IC 's FAS368M, FAS466, etc. The FAS466 (Fast Architecture SCSI Processor) processor is a high-performance SCSI engine launched by Qlogic in 1999. It is derived from the aluminum series of Qlogic's TEC450/452 triple embedded control. It can provide a synchronous transmission rate of Fast40, and its synchronous data wide bus transmission rate can reach 80MBps; it supports the advanced SCSI automatic configuration mode of layer 1 and layer 2 protocols; it has an embedded microcontroller inside, which can flexibly coordinate the SCSI job queue through programming. It can work in boot or target mode and support SCSI connections in single-ended or low- voltage differential mode. The biggest feature of FAS466 that distinguishes it from other SCSI protocol processors is that it uses a microprocessor and DMA interface structure, while the common SCSI protocol controller uses a PCI interface bus structure. This is one of the main reasons why FAS466 is used in this design. The use of a microprocessor and DMA interface structure can control the transmission through DSP, break away from the microcomputer platform, reduce the transmission bandwidth limitation, and make the data storage system very flexible and portable. FAS466 consists of four modules: SCSI controller, microcontroller, DMA interface and microprocessor interface. The external microprocessor controls FAS466 through the microprocessor interface, and the protocol controller accepts the operation instructions of the microprocessor, such as president, selection, disconnection, reset bus, etc. The SCSI controller provides flexible and effective underlying SCSI protocol control, and the microcontroller is responsible for controlling the transmission of data from the DMA interface to the SCSI hard disk and the coordination between various modules. The internal structure of FAS466 is shown in Figure 2. 1.4 Data Buffer In the input interface part of the device, a data cache unit is required. The purpose of the data cache is to prepare for the high-speed DMA transmission of SCSI so that the data transmission speed on both sides matches. The flow of data is generally one port in and one port out, and no signal processing is performed. Ordinary memory cannot be read while writing. Although dual-port random access memory RAM can also complete this task, it is not used because it requires complex address decoding circuits. The use of FIFO chips can remove the complex cache decoding circuit, greatly simplifying the system design. The cache unit is structurally equivalent to a first-in first-out (FIFO) queue, that is, the first data to arrive is stored first. In this design, the FIFO uses IDT's IDT72V2113 chip. 2 System Software Design Software design is the key and difficult part of this system design. It is responsible for the control and coordination of related hardware, and ultimately realizes SCSI protocol, hard disk control and DMA transmission. The software design is divided into two parts: SCSI control software and FPGA implementation of DMA controller. They are discussed separately below. 2.1 SCSI control software Generally speaking, to complete a data exchange, the arbitration, selection, message, command, data and status of the SCSI bus must be completed. These stages are realized by the microprocessor through the read and write control of the FAS466 register. The registers of FAS466 are mainly:     (1) Command register: DSP controls FAS466 to complete initialization, reset, bus allocation and reset, and the transition of various stages of the SCSI bus by writing corresponding instructions to the command register.     (2) FIFO register: This is a 128-byte dual-port RAM. The data exchange between the SCSI hard disk and FAS466 is completed through the FIFO register of FIF016 words (depth).     (3) Transfer count register: It is a subtraction counter used to store the number of bytes of a DMA data transfer.     (4) Interrupt register: The DSP uses the FAS466 interrupt register to understand the execution status of the SCSI command and thus determine the execution direction of the program.




























The SCSI control software flow is shown in Figure 3. First, the SCSI controller is initialized, and then the SCSI controller and the SCSI hard disk establish a synchronous transmission protocol. Only when the hard disk is ready can various SCSI commands such as read and write be sent, and various unexpected situations are handled at the same time.



2.2 FPGA Implementation Design of DMA Controller

The FAS466 external DMA controller is implemented by FPGA. FAS466 effectively requests data transmission through the DREQ signal. When the DMA controller detects that DREQ is valid and the external FIF0 is not empty, it makes DAC K valid and notifies FAS466 to start DMA transmission. The state machine of the DMA controller is shown in Figure 4.



In addition to implementing the external DMA controller of FAS466, FPGA also implements part of the logic and other logic control between FAS466 and the external microprocessor. The internal logic function module of FPGA is shown in Figure 5.

Based on the FAST-40 SCSI protocol, this paper designs the software and hardware of the real-time high-speed digital video SCSI storage system. Using FAS466 as a SCSI controller to realize the initiator function, control two SCSI hard disks to realize direct storage, and make full use of the bandwidth of the SCSI bus, thereby greatly improving the efficiency of the system. A relatively complete and practical direct storage structure system has been initially established, achieving a storage flow of 70MBps. This has laid a good foundation for solving the real-time storage of large-array, high-frame-rate CCD data. The solution of this technology will greatly promote the application and development in scientific research, military technology, especially in aerospace, aerial reconnaissance and high-speed data recording.