Liquid crystal display simulation KS0713 and its application

Overview

KS0713 is a small, large-scale integrated dot matrix LCD module with a driver and controller. Its appearance size is 42mm×39mm, with 29 external pins. It is directly controlled by the single-chip microcomputer, receives 8-bit serial or parallel data, and can display and store data in the data memory (DDRAM) on the module. Since the data display unit in DDRAM has a one-to-one correspondence with the dot matrix unit of the LCD screen, and the read and write operations of the KS0713 LCD module data are not controlled by an external clock, the display of KS0713 has high flexibility. The KS0713 LCD module has a necessary power drive circuit for the LCD, so that the module function can be realized with the smallest components and the smallest power consumption.
 

       
       1. Basic principles

       1. Pin Description

       Table 1 describes the pins of KS0713 and their functions.

       Table 1 KS0713 pin description

2. Main structure of KS0713 LCD module

(1) Display data memory (DDRAM)

DDRAM is used to store the display data of the liquid crystal. It is an address space with 65 rows and 132 columns. The 65 rows constitute 9 pages, of which the first 8 pages are composed of 8 columns (DB0~DB7), and the 9th page is a single row (only DB0). The display data DB0~DB7 is sent through the data port of the microcontroller, and is directly read or written to the 8 rows corresponding to each page through DB0~DB7; at the same time, each dot matrix can be determined by determining the page address and column address. While writing data to DDRAM, the corresponding dot matrix on the LCD screen is displayed, as shown in Figure 1.

(2) Page address circuit

The function of the page address circuit is to provide the page address for the display data memory. The page address is determined by sending the page control word to a 4-bit page address register. For example: on page 8, when DB3 is high, DB2, DB1 and DB0 are low.
 

           (3) Row address circuit

The row address circuit provides the row address for the DDRAM according to the display start row (COM0), so by changing the row address, the screen can be scrolled and switched without changing the on-chip RAM. The page address is changed through the row address register. It is only changed by the initial display row instruction and the 6-bit counting circuit. The contents of the register are automatically copied to the row counter when the LCD starts each frame.

(4) Column address circuit

The column address circuit provides the column address for DDRAM. It has an 8-bit pre-settable counter. When the MSB/LSB instruction to set the column address is sent, Y7~Y0 is updated (see the control word description for details); when there is a read or write instruction, the column address will be increased by 1 each time, so that the microcontroller can continuously transmit display data. However, the 8-bit counter is in a locked state when the MSB/LSB is not set. At this time, its lock value is any number greater than 84H, and the automatic increase function cannot be realized. Once the MSB/LSB is set again, the counter can be unlocked. The column address counter is independent of the page address register (see Table 2). The ADC selection instruction can convert the correspondence between the column address and the display column, as shown in Figure 2.

Table 2 Instruction control word table

(5) Liquid crystal display circuit

The LCD display circuit has an on-chip oscillator, and the oscillation frequency is independent of VDD. The output signal of the oscillator is used for voltage conversion and the timing generation circuit of the LCD display. Some signals of the timing generation circuit are used for LCD display. The clock signal of the LCD display is generated by the oscillating clock, which provides the clock signal for the row counter and the display data latch. The row address of the on-chip RAM is generated synchronously with the LCD display clock signal, and the 132-bit display data is synchronously latched into the display data latch circuit according to the display clock signal.