74595 Appearance drawing______
QB--|1 16|--VCC
QC--|2 15|--QA
QD--|3 14|--SI
QE--|4 13|--/G
QF--|5 12|--RCK
QG--|6 11|--SCK
QH--|7 10|--/SCLR
GND-|8 9|-- QH'
|_____|
Data terminal of 74595:
QA--QH: 8-bit parallel output terminal, which can directly control the 8 segments of the digital tube.
QH': cascade output terminal. I will connect it to the SI terminal of the next 595.
SI: serial data input terminal.
74595 control terminal description:
/SCLR (pin 10): When the low point is normal, the data of the shift register is cleared. I usually connect it to Vcc.
SCK (pin 11): The data of the data register is shifted on the rising edge. QA-->QB-->QC-->...-->QH; the data of the shift register remains unchanged on the falling edge. (Pulse width: at 5V, it is enough to be greater than tens of nanoseconds. I usually choose microseconds)
RCK (pin 12): The data of the shift register enters the data storage register on the rising edge, and the data of the storage register remains unchanged on the falling edge. I usually set RCK to a low point. When the shift is completed, a positive pulse is generated at the RCK terminal (at 5V, it is enough to be greater than tens of nanoseconds. I usually choose microseconds) to update the display data.
/G (pin 13): When the high level is high, the output is prohibited (high impedance state). If the pins of the microcontroller are not tight, it can be easily controlled by one pin to produce flashing and extinguishing effects. It saves time and effort than shifting control through the data terminal.
Note 1) 74164 and 74595 have similar functions, both are 8-bit serial input to parallel output shift registers. The driving current of 74164 (25mA) is smaller than that of 74595 (35mA), and it has 14 pins and is smaller in size.
2) The main advantage of 74595 is that it has a data storage register. During the shifting process, the data at the output end can remain unchanged. This is very useful in situations where the serial speed is slow, and the digital tube does not flicker.
3) 595 is a serial input and parallel output shift register with a latch function. It is very simple to use. In normal use, SCLR is high and G is low. Every time a bit of data is input from SER, the serial input 595 is a serial input and parallel output shift register with a latch function. It is very simple to use, as shown in the truth table below. In normal use, SCLR is high and G is low. Each time a bit of data is input from SER, the rising edge of the serial input clock SCK is valid once, until the eight bits of data are input, the rising edge of the output clock is valid once, at this time, the input data is sent to the output end.
In fact, after reading so much information about 595, I don't think it's difficult. The key is to understand its timing diagram. In the final analysis, it's the following three steps (quote):
Step 1: Purpose: Move the bit data to be input into the 74HC595 data input terminal.
Method: Send the bit data to P1.0.
Step 2: Purpose: To shift the bit data into 74HC595 one by one, that is, data serialization
method: P1.2 generates a rising edge, and the data on P1.0 is shifted into 74HC595, from low to high.
Step 3: Purpose: parallel output of data. That is, data parallel output
method: P1.1 generates a rising edge, and the data that has been shifted into the data register on P1.0
is sent to the output latch.
Explanation: From the above analysis, it can be seen that the generation of a rising edge from P1.2 (data input) and the generation of a rising edge from P1.1
(data output) are two independent processes, which do not interfere with each other in actual application. That is,
data can be input while data is output.
The specific programming method is
For example: 3FH is stored in R0, and the LED digital tube displays "0"
;*****Interface definition:
DS_595 EQU P1.0 ;Serial data input (595-14)
CH_595 EQU P1.2 ;Shift clock pulse (595-11)
CT_595 EQU P1.1 ;Output latch control pulse (595-12)
;*****Latch the data in the shift register to the output register and display
OUT_595:
CALL WR_595 ;Call the shift register to receive a byte of data subroutine
CLR CT_595 ;Pull down the latch control pulse
NOP
NOP
SETB CT_595 ;The rising edge sends the data to the output latch, and the LED digital tube displays "0"
NOP
NOP
CLR CT_595
RET
;*****The shift register receives a byte (such as 3FH) of data Subroutine
WR_595:
MOV R4,#08H ;One byte of data (8 bits)
MOV A,R0 ;R0 stores the data to be sent in 3FH
LOOP:
;The first step: prepare to move in 74HC595 data
RLC A ;Data shift
MOV DS_595,C ;Send data to the serial data input terminal (P1.0)
;The second step: generate a rising edge to move data into 74HC595
CLR CH_595 ;Pull down the shift clock
NOP
NOP
setb CH_595 ;Rising edge shift occurs (move in a data)
DJNZ R4, LOOP; One byte of data has not been moved yet, continue
with RET
The cascaded application of
74HC595 is mainly used in dot matrix screens. Take 16*16 dot matrix as an example: a row of two bytes (16 bits) is transmitted,
such as 06H and 3FH. The method is:
1. Send data 3FH first, then 06H.
2. After cascade serial input, 3FH is in IC 2 and 06H is in IC1. The application is shown in Figure 2.
3. Then send the latch clock, the data is latched and displayed on the parallel output ports of IC1 and IC2.
Programming method:
Data is in 30H and 31H
; MOV 30H, #3FH
; MOV 31H, #06H
;*****Interface definition:
DS_595 EQU P1.0 ;Serial data input (595-14)
CH_595 EQU P1.2 ;Shift clock pulse (595-11)
CT_595 EQU P1.1 ;Output latch control pulse (595-12)
;*****Serial input 16-bit data
MOV R0,30H
CALL WR_595 ;Serial input 3FH
nop
NOP
MOV R0,31H
CALL WR_595 ;Serial input 06H
NOP
NOP
SETB CT_595 ;The rising edge sends data to the output latch and displays
NOP
NOP
CLR CT_595
RET
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