Section 5: PIC series microcontroller data memory

PIC16C5X uses the data memory RAM as registers to make addressing simple and clear. They can be divided into operation registers, I/O registers, general registers and special function registers in terms of function. Their organizational structure is shown in Figure 1.4: These registers are represented by codes F0~F79. F0~F4 are operation registers, F5-F7 are I/O registers, and the rest are general registers. The addresses of special function registers are not transparent to users.

§1.5.1 Register Operation

1. F0 indirect address register

    addressing F0 actually means indirect addressing. The actual address is the content of register select register F4.

Example: MOVLW 10　
MOVWF f4; 10→f4
MOVLW 55　
MOVWF f0; 55→f10

2. F1 Real-time clock/count register (RTCC ) This

    register is an 8-bit counter. Like other registers, it can be read and written by the program. It is used to count the pulses applied to the RTCC pin or to count the internal clock (acting as a timer).

    It can be seen from the figure above that the RTCC working state is controlled by the OPTION register (see §1.5.4), where the RTS bit of the OPTION register is used to select the counting signal source of the RTCC. When RTS is "1", the signal source is the internal clock, and when RTS is "0", the signal source is the external signal from the RTCC pin. The PSA bit of the OPTION register controls the prescaler allocation object. When the PSA bit is "1", the 8-bit programmable pre-allocation is to the RTCC, that is, the external or internal signal is divided by the prescaler before being output to the RTCC. The division ratio of the prescaler is determined by PS0~PS2 in OPTION. At this time, the instructions involving writing the f1 (RTCC) register will clear the prescaler at the same time. However, it should be noted that the content of the OPTION register remains unchanged, that is, the allocation object, division ratio, etc. remain unchanged. The RTE bit of OPTION is used to select the external counting pulse trigger edge. When RTE is "1", it is a falling edge trigger, and when it is "0", it is a rising edge trigger.

    The RTCC counter counts in an incremental manner. When the count reaches FFH, it will automatically reset to zero after the next count occurs and start counting again, and the cycle continues. The response delay time of RTCC to its input pulse signal is 2 machine cycles , regardless of whether the input pulse is an internal clock, an external signal, or the output of a prescaler. The response timing is shown in Figure 1.6.

    The sampling period of RTCC to external signals is 2 oscillation cycles. Therefore, when the prescaler is not used, the pulse width applied to the RTCC pin must not be less than 2 oscillation cycles, that is, 1/2 instruction cycle. Similarly, when the prescaler is used, the output pulse period of the prescaler must not be less than the instruction cycle, so the maximum input frequency of the prescaler can reach N.fosc/4, where N is the division ratio of the prescaler, but it must not be greater than 50M Hz .

    When the RTCC uses the internal clock signal, if there is no prescaler, the RTCC value increases by 1 with the instruction beat. When a value is written to RTCC, the value of RTCC will not change in the next two instruction beats, and will only start to increase from the third instruction beat, as shown in the figure below.

    It should be noted that although PIC does not have strict requirements on the signal width applied to the RTCC signal terminal, if the high level or low level is maintained for too short a time, the RTCC may not detect the signal. Generally, the signal width is required to be greater than 10nS.

3. F2 Program Counter (PC)

    The program counter PC can address up to 2K of program memory. Table 1.3 lists the PC length and stack length of various PIC16C5X models.

    Once the microcontroller is reset (RESET), the value of F2 is set to "1". Unless an address jump instruction is executed, after an instruction is executed, the value of F2 (PC) will be incremented by 1 to point to the next instruction.
The following instructions may change the value of PC:
   a. "GOTO" instruction. It can directly write (change) the lower 9 bits of PC. For PIC16C56/57/58, the PA1 and PAO bits of the status register F3 will be placed in the upper two bits of PC. The "GOTO" instruction shown can jump to any place in the program memory.
   b. "CALL" instruction. It can directly write the lower 8 bits of PC and clear the 9th bit of PC. For PIC16C56/57/58, the PA1 and PAO bits of the status register F3 will be placed in the upper two bits of PC (10th and 11th bits).
   c. "RETLW" instruction. It writes the value of the stack item (stack 1) to PC.
   d. "MOVWF F2" instruction. It places the contents of the W register into PC.
   e. "ADDWF F2" instruction. It adds 1 to the PC value and then adds it to the value of the W register, and writes the result to the PC.
    In the above b, d and e, the 9th bit of the PC is always cleared to 0. So when using these three instructions to generate program jumps, the subroutine or branch program should be placed at the upper address of each page (000-0FF, 200-2FF, 400-4FF, 600-6FF respectively).

4. F3 Status Register (STATUS)

    As shown in Figure 1.7, F3 contains the arithmetic status of the ALU, the RESET status, the program memory page address, etc. Except for the PD and TO bits in F3, all other bits can be set or cleared by instructions. Note that when you execute an instruction to change the F3 register, the situation in F3 may be beyond your expectations.

    Example: CLRF F3; clear F3 to zero

    The result you get is F3=000UU100 (U is unchanged) instead of all zeros as you might imagine. The two bits UU are PD and TO, which remain unchanged, while the other two bits are set to "1" due to the clear operation. So if you want to change the content of F3, it is recommended that you use the three instructions BCF, BSF and MOVWF, because their execution does not affect other status bits.

Example: MOVLW 0; 0→W
    MOVWF F3; clear all bits of F3 except PD and TO, then you can get F3=000UU000.

    For the effect of each instruction on the status bit, please refer to Chapter 2.
    In addition (ADDWF), C is the carry bit. In subtraction (SUBWF), C is the inverse of the borrow bit (Borrow).

Example: CLRF F10; F10=0
MOVLW 1; 1→W
SUBWF F10; F10-W=0-1=FFH→F10
C=0: The operation result is negative
Example: MOVLW 1; 1→W
MOVWF F10; F10=1
CLRW; W=0
SUBWF F10; F10-W=1-0=1→F10
C=1: The operation result is positive

    The PD and TO bits can be used to determine the cause of RESET. For example, determine whether RESET is caused by chip power-on, or by watchdog WDT timer overflow, or by a low level at the reset terminal, or by WDT waking up SLEEP.
Table 1.4 lists the events that affect the TO and PD bits. Table 1.5 lists the TO and PD bit states after various RESETs.

    It is sometimes necessary to determine where the RESET is caused. For example, when initializing the system, it is often necessary to determine whether the reset is caused by power-on. If it is not a power-on reset, no initialization is performed.
The functions of the page selection bits PA1 and PA0 have been described above. When RESET is performed, the PA0-PA2 bits are cleared to zero, so the program area page is automatically selected at page 0 after reset.

5. F4 Register Select Register (FSR)
a. PIC16C52/54/55/56
    Bits 0-4 of F4 are used to select 32 data registers in indirect addressing. Bits 5-7 are read-only and always set to 1. Please refer to the description of F0 register.
b. PIC16C57/58
    FSR<6:5> bits are used to select the current data register bank. PIC16C57 has 80 data registers, as shown in Figure 1.4. The 80 registers are divided into 4 banks (Bank0 to Bank3), and the physical location of the lower 16 registers of each bank is the same (refer to §1.5.3 description of general registers). When the 4th bit of FSR is "1", the upper 16 registers in a certain register bank must be selected according to the FSR<6:5> bits.

Note: When the chip is powered on and reset, FSR<6:5> is indeterminate, so it may point to any bank. Other resets keep the original value unchanged.
For specific programming skills, please refer to the description of §2.7.2 Programming Basics.

§1.5.2 I/O Registers

    PIC16C52/54/56/58 has two I/O ports RA, RB (F5, F6), PIC16C55/57 has three I/O ports RA, RB, RC (F5, F6, F7). Like other registers, they can be read and written by instructions. They are programmable bidirectional I/O ports, and the input/output state of each I/O terminal can be determined by the program. The control method is shown in Section 1.8.
After RESET, all I/O ports are set to input state (equal to high impedance state), that is, the I/O control registers (TR ISA , TRISB, TRISC) are all set to "1".

1. F5 (A port)

    4-bit I/O port register. Only the lower 4 bits can be used. The upper 4 bits are always defined as "0".

2. F6 (B port)

    8-bit I/O port register.

3. F7 (Port C)

    is an 8-bit I/O port register for PIC16C55/PIC16C57 and
    a general purpose register for PIC16C54/56/58.

§1.5.3 General registers

PIC16C54/56:
    07H～1FH
PIC16C55:
    08H～1FH
PIC16C57/58:

08H-0FH: Common general registers (addressable without bank selection).
　　　　10H-1FH: General registers of Bank0
20H-2FH: Physically equivalent to 00H-0FH.
　　　　30H-3FH: General registers of Bank1
40H-4FH: Physically equivalent to 00H-0FH.
　　　　50H-5FH: General registers of Bank2
60H-6FH: Physically equivalent to 00H-0FH.
　　　　70H-7FH: General registers of Bank3.
Please refer to Figure 1.4. For addressing of register banks, please refer to the F4 register description and the examples in Chapter 4.

§1.5.4 Special Function Registers

1. Working register (W)

    W is used to store the second operand in two-operand instructions, or for internal data transfer. The arithmetic logic unit ALU connects W to the register, and the result of the ALU operation can be sent to W for storage through the data bus.

2. I/O control register (TRISA, TRISB, TRISC)

    TRISA, TRISB, and TRISC correspond to I/O ports A, B, and C respectively. Among them, TRISA has only 4 bits, corresponding to port A. Executing the "TRIS f" instruction can put the value of W into the I/O control register to define the input/output state of each I/O terminal. When "1" is written, the corresponding I/O terminal is set to input state (high impedance state), and when "0" is written, the corresponding I/O terminal is set to output state. I/O control registers are all write-only registers, which are automatically set to all "1" after RESET, that is, all I/O ports are in input state.

3. Preset multiple/RTCC selection register (OPTION)

OPTION can be used to:
    a. Define the prescaler parameters of the prescaler.
    b. Assign the prescaler to RTCC or WDT. Note that the prescaler can only be assigned to one of RTCC or WDT, not both.
    c. Define the signal source of RTCC.
    d. Define the trigger edge of the RTCC signal source (rising edge trigger or falling edge trigger).

Figure 1.8 shows the meaning of each bit of OPTION.
    When the prescaler is assigned to RTCC, all instructions that write to the RTCC register, such as CLRF 1, MOVWF 1, etc., will clear the prescaler. Similarly, when assigned to WDT, instructions such as CLRWDT and SLEEP will clear the existing value in the prescaler to zero.
By executing the "OPTION" instruction, the W value can be placed in the OPTIOW register, and OPTION is set to all "1" after RESET.

Example: MOVLW 07H; W = 7
OPTION; 7 → OPTION; The prescaler (1:256) is assigned to RTCC. The RTCC signal source is the internal instruction clock cycle.