STM32 system initialization function

Publisher:SereneNature7Latest update time:2017-11-05 Source: eefocusKeywords:STM32 Reading articles on mobile phones Scan QR code
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Keil is a joint venture between two private companies, the United States and Germany

Acquired by ARM in 2005, so its support for ARM kernel should be great

ARM is the chip core solution for stm32, so keil also has good support for stm chips.

STM32F10x_StdPeriph_Lib_V3.5.0

This is a software development firmware library provided by ST specifically for the 10x series

First open the KEIL software, currently using v4.10

After creating the project, click the magic wand tool options for target

In the C/C++ options, define three symbols in the symbol preprocessor

USE_STDPERIPH_DRIVER, allows the use of standard peripheral drivers ------------------ basically unchanged

STM32F10X_CL, main chip is Internet type chip, 105 or 107-----------Change according to chip

USE_STM3210C_EVAL The development board used is STM3210C--------------Official development board only

In this way, after compiling the project, the software will automatically import the startup_stm32f10x_cl.s file according to the chip selection.

This startup file is officially provided and written in assembly language.

In line 156 of the file, it is written that the systeminit() function is called through this file

This function is in the system_stm32f10x.c file under the CMSIS group of the project

There are two functions in the file: systeminit and SystemCoreClockUpdate. The latter is used to change the kernel clock.

The following is the key point (it talks about how the systeminit function defines the clock and which clocks it defines)

Open the file system_stm32f10x.c, and its code is explained as follows:

The first is a chip selection definition. If the CL level chip is defined,

Then the predefined system clock frequency = 72M  

#define SYSCLK_FREQ_72MHz 72000000

Then ask whether the external SRAM is defined

Generally there is no external connection (this sentence can be ignored)

Then define the vector table offset 0x0 

If the external SRAM is defined before, it should be offset by 0X200

Then an array is defined: __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};

This array is only used in the SystemCoreClockUpdate function to reset the system kernel clock function. It is not used here, so you can ignore it.

This array is the 9 possible AHB prescaler selections, in bits 4 to 7 of RCC_CFGR

When we list its values, we find that there are 16 in total, and the first eight values ​​indicate no frequency division, that is, the first 8 0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

RCC_CFGR 7:4 This is the AHB prescaler configuration 

0xxx: SYSCLK is not divided

1000: SYSCLK divided by 2 1100: SYSCLK divided by 64

1001: SYSCLK divided by 4 1101: SYSCLK divided by 128

1010: SYSCLK divided by 8 1110: SYSCLK divided by 256

1011: SYSCLK divided by 16 1111: SYSCLK divided by 512

The following is the function systeminit

1 Enable HSI

2 Reset RCC_CFGR

3 Reset RCC_CR

4 Reset RCC_CIR

5 Call SetSysClock(); Set the system clock

   According to the chip selection function SetSysClockTo72();------------------//This is different for different chips

6 Run the function SetSysClockTo72();

   6.1 Enabling HSE

   6.2 Determine whether the external clock is running stably and continue if it is stable

   6.3 Enable external flash memory and configure related parameters (external here means outside the core, but it is still inside the chip)

        Introduced in 3.3.3 Embedded Flash Memory of the official reference manual

7 Set HCLK equal to system clock

8 Set PCLK2 equal to HCLK

9 Set PCLK1 equal to HCLK

10 Set PLL2 output clock

Setting the PREDIV1 output clock

11 Enable PLL2

12 Set the PLL clock frequency 

13 Enable PLL

14 Select PLL as the system clock source

So the systeminit function actually defines the first half of the clock tree. The second half needs to be defined in the user's C as needed.

The following results are obtained: Note that this is the setting for CL-level chips. If the chip is different, the results will be different.

HSE external high speed clock 25MHZ enable----------------------result

PREDIV2 Prescaler 2 1/5 -----------Process

PLL2MUL Phase-locked loop 2 frequency multiplier 8 -----------Process

PLL2CLK Phase-locked loop 2 clock 40MHZ Enable -------------------------- Result

PREDIV1 Prescaler 1 1/5 -----------Process  

PLLMUL Phase-locked loop frequency multiplier 8 -----------Process

PLLCLK Phase-locked loop clock 72MHZ Enable-----------------------Result  

SYSCLK system clock 72MHZ ---------------------------Result

HCLK High-level peripheral clock 72MHZ 9 peripherals are not enabled------------Result

PCLK1 Peripheral clock 1 36MHZ 20 peripherals are not enabled-----------Result

PCLK2 peripheral clock 2 72MHZ 11 peripherals are not enabled-----------Result

For example, the power supply bureau has sent electricity to your home through a transformer with a different voltage.

But the switches at home are not turned on yet. You can turn them on yourself when you need them. This is more energy-efficient.


Keywords:STM32 Reference address:STM32 system initialization function

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