STM32 study notes: FSMC details

FSMC (Flexible Static Memory Controller) is a new memory expansion technology used by the STM32 series. It has unique advantages in external memory expansion and can easily expand different types of large-capacity static memories according to system application needs .

After using the FSMC controller, the FSMC_A[25:0] provided by the FSMC can be used as the address line, and the FSMC_D[15:0] provided by the FSMC can be used as the data bus.

(1) When the storage data is set to 8 bits, (FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b)

    Each address bit corresponds to FSMC_A[25:0], and the data bit corresponds to FSMC_D[7:0]

(2) When the storage data is set to 16 bits, (FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b)

    Each address bit corresponds to FSMC_A[24:0], and the data bit corresponds to FSMC_D[15:0]

FSMC consists of 4 modules:

(1) AHB interface (including FSMC configuration register)

(2) NOR flash memory and PSRAM controller (when driving LCD, LCD is like a PSRAM with only two 16-bit storage spaces, one is DATA RAM and the other is CMD RAM)

(3) NAND flash memory and PC card controller

(4) External device interface

Note: FSMC can request AHB to perform data width operations. If the data width of the AHB operation is larger than the width of the external device (NOR or NAND or LCD), FSMC will split the AHB operation into several consecutive smaller data widths to adapt to the data width of the external device.

The FSMC address image for external devices starts from 0x6000 0000 and ends at 0x9FFF FFFF, with a total of 4 address blocks, each of which is 256M bytes. It can be seen that each address block is divided into 4 sub-address blocks, each of which is 64M in size. For the address image of NOR, we can determine which 64M sub-address block is currently being used by selecting HADDR[27:26], as shown in the table on the next page. The chip selects of these four sub-storage blocks are selected using NE[4:1]. The data line/address line/control line are shared.

NE1 ->Bank1 NE2->Bank2 NE3->Bank3 NE4->Bank4

If NE1 is connected, then

Each small block of NOR/PSRAM 64M

 The first block: 6000 0000h--63ff ffffh (When the DATA length is 8 bits, it is determined by the address line FSMC_A[25:0]; when the DATA length is 16 bits, it is determined by the address line FSMC_A[24:0])

 The second block: 6400 0000h--67ff ffffh

 The second block: 6800 0000h--6bff ffffh

 The third block: 6c00 0000h--6fff ffffh

Note: HADDR here is the internal AHB address line that needs to be converted to the external device. Each address corresponds to a byte unit. Therefore, if the address width of the external device is 8 bits, HADDR[25:0] corresponds to the STM32 CPU pin FSMC_A[25:0] one-to-one, and a maximum of 64M bytes of space can be accessed. If the address width of the external device is 16 bits, HADDR[25:1] corresponds to the STM32 CPU pin FSMC_A[24:0] one-to-one. When applied, the FSMC_A bus can be connected to the address bus pins of the memory or other peripherals.

Example: STM32F10XX FCMS controls LCD driver

 FSMC provides all LCD controller signals:
FSMC_D[16:0]