About the hardware interface and timing issues of Linux framebuffer and s3c2410

The formula of pixel clock:
VCLK = HCLK/[(CLKVAL+1)X2].
In this system, the value of HCLK is 100M HZ.
The following is the relationship between several parameters and the s3c2410fb_display data structure:
VBPD is the vertical back porch, which indicates the number of invalid rows after the vertical synchronization signal at the beginning of a frame of image, corresponding to upper_margin;
VFBD is the vertical front porch, which indicates the number of invalid rows before the vertical synchronization signal after the end of a frame of image, corresponding to lower_margin;
VSPW is the vertical sync pulse width, which indicates the width of the vertical synchronization pulse, calculated by the number of rows, corresponding to vsync_len;
HBPD is the horizontal back porch, which indicates the number of VCLKs from the falling edge of the horizontal synchronization signal to the beginning of valid data of a row, corresponding to left_margin;
HFPD is the horizontal front porth, which indicates the number of VCLKs from the end of valid data of a row to the beginning of the next horizontal synchronization signal, corresponding to right_margin;
HSPW is the horizontal sync pulse width represents the width of the horizontal synchronization signal, calculated by VCLK, corresponding to hsync_len;
according to the data sheet of LQ61D133, we can get the following data:
  left_margin = 48
  right_margin = 16
  hsync_len = 96
  upper_margin = 32
  lower_margin = 11
  vsync_len = 2
  pixclock = 39714
lcdcon1 : 17~8 CLKVAL 6~5 select the display mode 4~1 select the bpp mode 0 enable output
lcdcon2 : 31~24 VBPD 23~14 LINEVAL 13~6 VFPD 5~0 VSPW
lcdcon3 : 25~19 HBPD 18~8 HOZVAL 7~0 HFPD
lcdcon4 : 7~0 HSPW
lcdcon5 :