Design of High-Speed ​​Synchronous Data Acquisition System Based on ISA Bus

　　With the rapid development of large-scale integrated circuits, the performance of PCs is constantly improving. By embedding an intelligent function card with a high-performance microprocessor as the core in the expansion slot of the PC, a distributed control system with excellent comprehensive performance can be formed. This structural method can make full use of the control function of the microprocessor, the fast data processing capability of the PC, and the multi-tasking working mode. For this distributed control system, the host must frequently receive the data, working status and other information collected from the expansion card slave; send control commands or process data to the slave. There are many ways for this communication between the master and the slave, depending on the application conditions. However, in situations where the data transmission speed is high, the data volume is large, and information needs to be exchanged frequently, the dual-port shared RAM buffer method is the most appropriate.

　　In order to use a single-chip microcomputer to sample high-speed transient signals at the microsecond or even nanosecond level, a technology based on the ISA bus, GPS synchronous clock, and hardware circuits to achieve high-speed data acquisition, high-speed addressing, and storage is studied to ensure the real-time acquisition of high-speed transient signals. For the acquisition of high-speed transient signals with extremely fast changes and extremely short processes, high-speed A/D conversion units, a large number of data storage units, high-speed addressing, and fast storage are required.

　　Since the collected signals are high-frequency signals, the conventional method is limited by the operating speed of the microcontroller itself, which not only increases the cost, but also increases the difficulty of signal processing of high-frequency, long-distance multi-channel signals, and sometimes it is impossible to distinguish the authenticity of the collected signals. By effectively expanding the periphery of the 8051 microcontroller, the hardware is used to collect and store data during data collection, and the 8051 series microcontroller performs data processing and communication after the collection is completed, which better solves the contradiction between the two.

　　

　　The high-speed data acquisition board developed by the author has a sampling frequency of 20MSPS; the A/D conversion word length is 8 bits, and the sampling rate is variable; the storage capacity is 512K bytes, which complies with the ISA bus standard. It can be widely used in power measurement, relay protection and fault location, etc.

　　1 Basic working principle of hardware system

　　The hardware circuit block diagram is shown in Figure 1. It consists of CPU1 and CPU2 basic systems, video flicker ADC converter, cache RAM, dual-port RAM, address counter, sampling frequency control, timing control and decoding circuit.

　　The CPU uses the DS80C320 microcontroller as required. Under the condition of a clock frequency of 33MHz, the execution time of a single-cycle instruction is 110 nanoseconds, giving full play to the performance of the high-speed A/D conversion chip. The DS80C320 has three 16-bit timers/counters, two full-duplex serial ports, thirteen interrupt sources (six external interrupt ports), and two data pointers DPTR0 and DPTR1. At a 33MHz crystal oscillator, the output signal frequency of ALE is 8.25MHz.

　　CPU1 is mainly used for data collection and communication with the PC; CPU2 is used to receive GPS time messages, which can be read by CPU1 from the dual-port RAM2 connected to it at any time. High-speed dual-port RAM

　　IDT7130 (2K×8 bits) and IDT7134 (4K×8 bits) have internal judgment circuits to prevent conflicts caused by simultaneous operations on a certain unit.

　　IDT7134 is mainly used by CPU1 to store collected data, synchronization time information and working status, etc., for PC to access regularly, and also receives commands from the PC.

　　IDT7130 has a capacity of 2K bytes and is mainly used for CPU1 and CPU2 to exchange GPS synchronization clock information.

　　For high-speed data acquisition technology, the most important factors are the system resolution, accuracy and throughput rate. In particular, the system throughput rate is the most critical technical indicator that distinguishes high-speed data acquisition from general data acquisition. In the specific hardware implementation process, two aspects need to be considered: (1) the conversion time of the A/D converter; (2) the storage time of the converted data [2].

　　1.1 High-speed A/D conversion

　　The A/D conversion uses the flash ADC device AD9048, which has a maximum conversion rate of 35MSPS and a resolution of 8 bits. It is manufactured using a high-speed bipolar process, has a fast sampling rate, a wide bandwidth, no code loss, a small input capacitance (only 16pF), and low power consumption (500mW). The internal clock-locked comparator of the AD9048 allows the encoding logic circuit and the output buffer register to operate at a high speed of 35MSPS, and avoids the need for sample-and-hold circuits (S/H) and track-and-hold circuits (T/H) in most systems. The digital input, output and control levels are compatible with TTL. AD589, AD741, 2N3906, etc. form a voltage-regulating adjustable circuit, which is provided to the RB and RT grounding of the 9048. AD9618 is used as an input buffer amplifier [3]. Since the data output of the AD9048 does not have a three-state gate control, a 74LS241 is added to the output for three-state gate control. Whether the AD9048 works depends on the input conversion pulse signal, and sampling is performed on the rising edge of the pulse signal. The conversion pulse comes from the output of the 8254 frequency divider in the sampling frequency control circuit.

　　1.2 High-speed addressing

　　For high-speed data acquisition systems, A/D conversion should not be controlled by the CPU. Every time the ADC is converted, the control circuit sends a corresponding signal to write the ADC conversion result into a unit of the high-speed cache RAM, and then add 1 to the address counter until the address counter is full and generates a sampling end signal, blocks the RAM write signal, and uses the highest bit of the binary address generator to notify the host that the sampling is completed through an interrupt.

　　The address counter can be formed by cascading several synchronous registers according to the number of address bits. Five 74LS163s can form a 19-bit address formation circuit. The counter generates an address every time it receives a pulse. The initial value of the address can be cleared by the timing control circuit. If a circular address is used, after the count is full, the carry signal is used to force the synchronous preset level of the counter to change, so that the counter returns to the initial value and enters a new round of counting.

　　1.3 Fast Storage

　　The data transmission rate of the serial communication between the microcontroller and the host PC often cannot meet the real-time requirements; the maximum data transmission rate of the DMA channel does not exceed 5MB/s [1], which is obviously unable to meet the sampling speed of up to 20MB/s in this system. In order to solve the contradiction between high-speed data acquisition and low-speed data transmission, in the microcontroller system, the data storage uses dual-port RAM

　　IDT7134 (RAM1 in Figure 1). A 4K-byte buffer is established between the host PC and the MCU. The MCU only needs to store the pre-processed sample values ​​in the buffer through one port, and the host PC takes data from the buffer through another port. This solves the contradiction between high-speed sampling and low-speed data transmission, and can meet the requirements of real-time acquisition and control.

　　

　　1.4 Bus Control

　　The single-chip system bus is connected with several RAM or I/O ports. Addressing and data transmission are realized by the CPU issuing instructions through the system bus. For high-speed data acquisition, in order to improve the addressing and data transmission speed and avoid bus conflicts or blockages, a local bus must be established. The system bus and the local bus should be both distinguished and unified, isolated and combined, and connected to each other through reasonable control logic.

　　The basic principle of bus arbitration is to use different lengths of read and write cycles for different bus requests, so that the bus occupation time of each user is interlaced, and the user does not feel the existence of arbitration. In the memory mapping transmission mode, A/D continuously writes the converted data into the cache RAM, and the CPU reads the data from the cache RAM to the dual-port RAM1 according to the needs of data processing. The dual-port RAM1 also needs to refresh all units. These three operations all occupy the data and address buses on the card. However, the time they occur is random, so the occupation of the bus will inevitably cause conflicts. The function of the bus arbitration circuit is to coordinate these three operations. Here, five 74LS241 two-to-one switches are used to coordinate the conflict between the address counter and the CPU1 reading the cache RAM address, and two 74LS241s coordinate the conflict between the cache RAM and the data transmission between the AD9048 and the dual-port RAM.

　　1.5 PC bus interface technology

　　It is difficult for the PC system bus to address the 4KB dual-port RAM. This data acquisition card uses the PC bus, also known as the 8-bit ISA bus. It is flexible to use and is easy to form an interface circuit with an 8-bit single-chip. There are 62 leads, divided into five categories: address lines, data lines, control lines, auxiliary and power lines. This data acquisition card only uses a part of the leads: 8 data lines, 10 address lines, IOR and IOW control lines, and power lines. The detailed block diagram of the decoding circuit is shown in Figure 2.

　　This data acquisition card uses three port addresses 308H, 309H, and 30AH to achieve 4KB addressing of the on-board cache. The decoding circuit here uses GAL20V8 and two 74HC574s. When the PC wants to access a certain address, it first writes the low 8-bit address of the dual-port RAM. At this time, the output signal of GAL20V8 selects 74HC574 (right), latches the data on PC-DB, and forms the low 8-bit address Addrl of the dual-port RAM; then writes the high 8-bit address of the dual-port RAM. The output signal of GAL20V8 selects 74HC574 (left), latches the data on PC-DB, and forms the high 8-bit address Addrh of the dual-port RAM. Finally, by selecting the chip select terminal cs of the dual-port RAM, a data read/write process is completed.

　　1.6 Sampling frequency control circuit

　　The sampling frequency mining circuit is composed of a crystal oscillator, a programmable frequency divider 8254 and some control circuits. 8254 is a programmable frequency divider with an operating frequency of 8MHz to 20MHz. Different frequencies can be output through different frequency division numbers, and the frequency division number is between 2 and 65535. Its output is controlled by a trigger control circuit. Its output clock is sent to the address counter, the write signal control circuit of the cache RAM and the conversion pulse input of the AD9048.

　　2 System Software Design

　　The main function of the system software is to provide users with a good operating environment and respond to user commands in a timely manner. The user operation interface adopts Visual

　　Basic language is used. Through a series of commands. The user interface adopts Visual

　　Basic language is used to write the software. By using a series of command buttons, the waveform of the actual signal collected by the power system, the time of the fault, etc. are mapped to the computer screen, so that the user can have an intuitive understanding of the collected information. By using the software virtual hardware operation interface, the powerful computing function of the computer, the flexible and changeable software advantages and the powerful display function of VGA can be fully utilized. In order to facilitate the expansion of the system and the reuse of software, the entire software is divided into several relatively independent functional modules, the code within the module is encapsulated, and a unified interface specification is established between each other.

　　

　　Since this system not only has high-level, disk-oriented operations, but also many operations that directly control hardware, TURBO is used.

　　C and assembly language mixed programming technology, each module uses the appropriate language according to the operation object. In this way, the advantages of high-level language programming, such as convenience and good structure, and assembly language, such as speed, flexibility and strong pertinence, can be utilized at the same time.

　　The system software block diagram is shown in Figure 3.

　　The hardware driver is used to complete the operation of the hardware, and is written in assembly language. Before using the system, run this program first. The program modifies the PC system interrupt, resides in the memory after running, and interfaces with the main program through standard soft interrupts.

　　The high-speed graphics unit directly operates the PC's VGA registers and display memory, and displays the sampled signals at a relatively fast speed by calling related functions and the VGA graphics library.

　　The data analysis unit is mainly used to post-process the sampled signal. It can complete data processing functions such as wavelet transform, signal singularity detection, spectrum analysis and correlation analysis, and display the time domain signal and analysis structure with curves through the waveform output unit.

　　The whole system provides users with a fast graphical operation interface based on WINDOWS. The system master program coordinates the operation of the whole system and controls the hardware to run automatically. The system interface includes a high-speed viewport and command buttons for waveform display, etc., which can intuitively observe the real-time collected data waveform, amplitude and the time of fault occurrence through simple operations. At the same time, it provides an external software interface, and users can organize data in the specified format and process data using the powerful data analysis function of this system.

　　This high-speed acquisition card has the characteristics of high sampling rate, flexible operation mode, high synchronization clock accuracy and compliance with ISA bus standards. With DS80C320 microcontroller as the core, GPS synchronization time is adopted, and appropriate peripheral equipment and reasonable bus control technology are used to achieve high-speed data acquisition. At the same time, it has the functions of digital storage oscilloscope and data analysis capabilities, and can be widely used in power measurement, power system fault location and relay protection fields.