Working principle of 8051 microcontroller I/O port

The structure of one of the 8 bits of port P0 is shown in the figure below:

As can be seen from the above figure, the P0 port is composed of a latch, an input buffer, a switch, a NAND gate, an AND gate and a field effect transistor drive circuit.

Next, we analyze the various parts that make up the P0 port:
First look at the input buffer: In the P0 port, there are two three-state buffers, whose output terminals can be high level, low level, and there is also a high-impedance state (or called the prohibited state). The upper one is the buffer for reading the latch, and the lower one is the buffer for reading the pin, which reads the data on the P0.X pin. To make this three-state buffer effective, the data on the pin will be transmitted to the internal data bus.

D latch: In the 32 I/O lines of the 51 single-chip microcomputer, a D flip-flop is used to form a latch. The D terminal is the data input terminal, CP is the control terminal (that is, the timing control signal input terminal), Q is the output terminal, and Q is the reverse output terminal.

Multiplexer: In the 51 single-chip microcomputer, when there is no need for external memory expansion, the P0 port can be used as a general input and output port (i.e. I/O). For the 8031 ​​single-chip microcomputer (without internal ROM) or the program written exceeds the internal memory capacity of the single-chip microcomputer, when external memory expansion is required, the P0 port is used as the 'address/data' bus. This multiplexer selection switch is used to select whether to use it as a normal I/O port or as a 'data/address' bus. When the multiplexer is connected to the bottom, the P0 port is used as a normal I/O port. When the multiplexer is connected to the top, the P0 port is used as an 'address/data' bus.

Output drive part: The output of P0 port is a push-pull structure composed of two MOS tubes, that is, these two MOS tubes can only be turned on one at a time. When V1 is turned on, V2 is turned off, and when V2 is turned on, V1 is turned off.

   When the P0 port is used as an I/O port, the control signal of the multiplexer is 0 (low level), the V1 tube is cut off, and the multiplexer is connected to the non-Q end of the latch (that is, the P0 port is used as an I/O port line). When used as an address/data line, the control signal of the multiplexer is 1, the V1 tube is determined by the address/data line, and the multiplexer is connected to the address/data line.

Output process:

1. I/O output working process: When the write latch signal CP is valid, the signal of the data bus → the input terminal D of the latch → the reverse output Q non-terminal of the latch → the multiplexer → the gate of the V2 tube → the drain of V2 to the output terminal P0.X. At this time, the control signal of the multiplexer is low level 0, and the V1 tube is cut off, so when used as an output port, P0 is an open-drain output, similar to an OC gate. When driving a current load, an external pull-up resistor is required. The
following figure is a flow chart of outputting data from the internal data bus to the P0 port (red arrow).

2. Address output process

When the control signal is 1 and the address signal is "0", the AND gate outputs a low level and the V1 tube is cut off; the inverter outputs a high level, the V2 tube is turned on, and the address signal of the output pin is a low level.

On the contrary, when the control signal is "1" and the address signal is "1", the output of the "AND gate" is high level, the V1 tube is turned on; the inverter outputs low level, the V2 tube is turned off, and the address signal of the output pin is high level. Please see the figure below (blue font is level):

It can be seen that when outputting "address/data" information, V1 and V2 tubes are turned on alternately, and have a strong load capacity. They can be directly connected to the external memory without adding a bus driver.

3. Output process as data bus

If the instruction is to output data, such as MOVX @DPTR, A (transfer the contents of the accumulator to the external RAM through the P0 port data bus), the multiplexer "control" signal is '1', the "AND gate" is unlocked, and the workflow is similar to the output address signal. The data is output from the "address/data" line → inverter → V2 field effect transistor gate → V2 drain.

Input process:

1. I/O read pin working process:
     When reading data on the chip pin, the read pin buffer is opened and input through the internal data bus, please see the figure below (red header).

2. I/O read latch working process:

The state of the latch output Q is read by opening the read latch tri-state buffer, see the figure below (red arrow):

3. Read instruction code and data process when address/data

  Used as a data bus. When accessing the external program memory, after the P0 port outputs the low 8-bit address information, it will become a data bus to read the instruction code (input). During instruction fetching, the "control" signal is "0", the V1 tube is cut off, and the multiplexer also turns to the inverting output terminal Q of the latch; the CPU automatically writes 0FFH (11111111, that is, writes a high level '1' to the D latch) to the P0 port latch, turning off the V2 tube. Under the control of the read pin signal, the instruction code is read to the internal bus through the read pin tri-state gate circuit. This process is the same as the I/O read pin process.

In the input state, the signals read from the latch and the pin are generally consistent, but there are exceptions. For example, when a low level is output from the internal bus, the latch Q = 0, Q non = 1, the field effect transistor T2 is turned on, and the port line is in a low level state. At this time, no matter whether the external signal on the port line is low or high, the signal read from the pin to the microcontroller is low, so the signal on the port pin cannot be read correctly. For another example, when a high level is output from the internal bus, the latch Q = 1, Q non = 0, and the field effect transistor T2 is turned off. If the external pin signal is low, the signal read from the pin is different from the signal read from the latch. For this reason, the 8031 ​​microcontroller has the following agreement on the input operation of ports P0-P3: For this reason, the 8051 microcontroller has the following agreement on the input operation of ports P0-P3: For instructions belonging to the read-modify-write mode, the signal is read from the latch, and other instructions read the signal from the port pin line. The characteristic of the read-modify-write instruction is that the signal is input (read) from the port, calculated (modified) in the microcontroller, and then output (written) to the port. The reason for this arrangement is that the read-modify-write instruction needs to obtain the original output state of the port, modify it and then output it. Reading the latch instead of reading the pin can avoid the original port state being read incorrectly due to external circuit reasons. When P0 is used as the address/data bus, before reading the instruction code or inputting data, the CPU automatically writes 0FFH to the P0 port latch, destroying the original state of the P0 port. Therefore, it can no longer be used as a general I/O port. Be sure to pay attention when designing the system, that is, the program can no longer contain instructions that use the P0 port as an operand (including source operands and destination operands).

2. Structure and working principle of P1 port

As can be seen from the figure, the main difference between the P1 port and the P0 port is that the P1 port uses an internal pull-up resistor R instead of the field effect transistor T1 of the P0 port, and the output information only comes from the internal bus. The data output by the internal bus is inverted by the latch and the field effect transistor, and then latched on the port line. Therefore, the P1 port is a static port with output latch. To correctly read external information from the pin, the field effect transistor must be turned off first so that the state of the pin can be determined by the external input information. For this reason, before reading the pin, l must be written to the port first. The input/output port with this operating characteristic is called a quasi-bidirectional I/O port. P1, P2, and P3 of the 8051 microcontroller are all quasi-bidirectional ports. Since the P0 port has a three-state output function, the port line is already in a high-impedance state before input, and there is no need to write l before performing a read operation. After the microcontroller is reset, each port has been automatically written with 1, and at this time, input operations can be performed directly. If 0 has been output to the P1-P3 port line during the application of the port, when you want to input again, you must first write 1 and then read the pin to get the correct information. In addition, depending on the input instruction, the P1 port also has the distinction of reading latches and reading pins.

3. Structure and working principle of P2 port:

As can be seen from the figure, the P2 port has both a pull-up resistor and a switch MUX in the chip, so the P2 port has the characteristics of both the P0 port and the P1 port in terms of function. This is mainly reflected in the output function. When the switch is turned down, the one-bit data output from the internal bus is inverted by the inverter and the field effect transistor and output on the port pin line; when the multiplexer is turned up, the one-bit address signal output is also inverted by the inverter and the field effect transistor and output on the port pin line.
For the 8031 ​​microcontroller, an external program memory must be connected to form an application circuit (or our application circuit has expanded the external memory), and the P2 port is used to periodically output the address (high 8-bit address) of fetching instructions from the external memory. Therefore, the multiplexer of the P2 port is always switching, and the data from the internal bus and the address from the address signal line are output in a time-sharing manner. Therefore, the P2 port is a dynamic I/O port. Although the output data is latched, it does not appear stably on the port line. In fact, the data output here is often also a kind of address, but it is the high 8-bit address of the external RAM.
     In terms of input function, the P2 port is the same as the P0 and H ports, with read pins and read latches, and the P2 port is also a quasi-bidirectional port.
It can be seen that the main features of the P2 port include:
① It cannot output static data;
② It outputs the high 8-bit address of the external program memory;
② When executing the MOVX instruction, it also outputs the high-bit address of the external RAM, so the P2 port is called a dynamic address port.

Since port P2 can be used as an I/O port or as an address bus, let's analyze its two working states below.

1. Working process when used as an I/O port
    When there is no external program memory or although there is an external data memory, it is not greater than 256B, that is, when the high 8-bit address is not required (in this case, the external data memory cannot be read and written through the data address register DPTR), the P2 port can be used as an I/O port. At this time, the "control" signal is "0", the multiplexer turns to the latch in-phase output terminal Q, and the output signal is output through the internal bus → latch in-phase output terminal Q → inverter → V2 tube gate → V2 tube 9 drain.
    Since the V2 drain has a pull-up resistor, it can provide a certain pull-up current, and the load capacity is about 8 TTL NAND gates; before being used as an output port, it is also necessary to write "1" to the latch to make the inverter output a low level and the V2 tube cut off, that is, the pin is high when it is suspended to prevent the pin from being clamped at a low level. After the read pin is valid, the input information is sent to the internal data bus through the read pin tri-state gate circuit.

2. Working process when used as address bus
    When P2 port is used as address bus, the "control" signal is '1', the multiplexer turns to the address line (i.e., it is turned on upward), and the address information is output through the inverter → V2 tube gate → drain. Since P2 port outputs the high 8-bit address, unlike P0 port, it does not need to be used in time sharing, so the address information on P2 port (A15~A8 on the program memory) is stored for a long time in the high 8-bit DPH of the data address register without latching.

4. Structure and working principle of P3 port

The P3 port is a multi-function port. In addition to being an I/O port, it also has a second function. The one-bit structure of the P3 port is shown in the figure below.

As can be seen from the figure above, the structures of the P3 port and the P1 port are similar, the only difference is that each port line of the P3 port has two function options. When in the first function, the second output function line is 1. At this time, the internal bus signal is input/output through the latch and the field effect tube. Its function is the same as that of the P1 port, and it is also a static quasi-bidirectional I/O port. When in the second function, the latch outputs 1 and outputs a specific included signal through the second output function line. In terms of input, the pin signal can be read through the buffer, and the specific second function signal in the chip can also be read through the alternative input function. Since the output signal is latched and has dual functions, the P3 port is a static dual-function port.

The conditions for making the P3 terminal lines in the second function are:

1. Serial I/O is in operation (RXD, TXD);

2. Open the internal interrupt (INT0, INT1);

3. The timer/counter is in external counting state (T0, T1)

4. Execute instructions for reading and writing external RAM (RD, WR)

     In the application, if the second function of each bit of the P3 port is not set (the generation of WR and RD signals does not need to be set), the P3 port line is automatically in the first function state, that is, the working state of the static I/O port. In more cases, according to the needs of the application, several port lines are set to the second function, while the other port lines are in the first function operation state. In this case, it is not appropriate to perform byte operations on the P3 port, and bit operations must be used.

4. Driving Capability

The P0 port can drive 8 LSTTL loads. If you need to increase the load capacity, you can add a bus driver to the P0 bus. The P1, P2, and P3 ports can each drive 4 LSTTL loads. Since the P0-P3 ports have been mapped to the P0-P3 port registers in the special function registers, the read/write of these port registers realizes the input/output of information from the corresponding ports. For example:
MOV A, P1; input the information on the P1 port line to A
MOV P1, A; output the content of A from the P1 port
MOV P3, #0FFH; make the P3 port line positions l