STM8 reset

STM8S has 9 reset sources:

External reset generated by NRST pin 
Power-on reset (POR) 
Power-down reset (BOR)
Independent watchdog reset
Window watchdog reset
Software reset
SWIM reset
Illegal opcode reset
EMS reset: reset generated when some key registers are corrupted or loaded incorrectly

All reset sources ultimately act on the NRST pin and remain low during the reset process. The reset entry vector is located at a fixed address 6000h in the memory map.

Reset Circuit

The reset pin NRST has an internal weak pull-up resistor RPU, which can be used as an input or an open-drain output.
A low-level pulse with a minimum width of 500ns on the reset pin can generate an external reset. The reset detection is asynchronous, so it is possible to enter the reset state even if the MCU is in Halt mode. The
reset pin can also be used as an open-drain output to reset external devices.
Regardless of the internal reset source, once reset, the internal reset circuit will generate a reset pulse with a pulse width of at least 20us.
When no external reset occurs, the internal weak pull-up resistor ensures that the reset pin is at a high level.
Please refer to Figure 11 and the electrical characteristics parameter section in the data sheet for more details.

Internal reset source

 

In addition to the power-on reset (POR) and power-down reset (BOR), each internal reset source has a flag bit corresponding to it in the reset status register. At reset, these flag bits are set separately according to the reset source that caused the reset. Therefore, these flag bits can be used to indicate the reset source that caused the last reset. The flag bit can be cleared by software writing '1'.

Power-on reset (POR) and power-down reset (BOR)
During power-on of the STM8, the POR keeps the device in reset until the supply voltage (VDD and VDDIO) reaches the start voltage of the BOR. At this point, the BOR reset replaces the POR and the POR is automatically turned off.
The BOR reset continues until the supply voltage reaches the operating voltage. For details, please refer to the electrical characteristics section of the data sheet.
When the operating voltage drops below the threshold VIT-, the BOR will also generate a reset, after which the POR module will be ready to respond to the next power-on reset.
Voltage hysteresis is used to ensure clear detection of voltage rise and fall.
Even if the MCU is in low power mode, the BOR always remains active.

  

Watchdog reset
For details, see 14 Independent Watchdog (IWDG) and 15 Window Watchdog (WWDG). 
Software reset
The application can trigger a reset by clearing the T6 bit in the register WWDG_CR, see 15 Window Watchdog (WWDG).
SWIM reset
An external device connected to the SWIM interface can generate an MCU reset through the SWIM module.
Illegal opcode reset
In order to improve the reliability of STM8 devices and prevent unexpected behavior, an illegal opcode detection system is used. If the executed code does not match any opcode or preset byte, a reset is generated. This function, in conjunction with the watchdog, allows the device to recover from an unexpected error or interference.
Note: An illegal combination of a valid preset byte and a valid opcode will not generate a reset.
EMS reset
In order to avoid accidental write operations or system hangs caused by electromagnetic interference to the application, most key registers have a complementary register corresponding to them. The system will automatically detect whether these key registers match their complementary registers. If they do not match, an EMS reset is generated to restore the application to normal operation.