51 Notes on STC

1. Basic characteristics

        Working frequency range: 0-35MHZ, each machine cycle is one clock cycle, the instruction execution speed is comprehensively improved, the fastest is increased by 24 times, and the slowest is increased by 3 times.

        Internally integrated MAX810 dedicated reset circuit, built-in power failure detection circuit for VCC power failure detection;

        Clock source: external high-precision crystal/clock, internal R/C oscillator; users choose to use external crystal/clock or internal R/C oscillator when downloading the program;

2. Memory

1) Program memory

        User program memory space: 1/2/3/4/5/6/8/16/20/32/40/48/52/56/60/62K bytes

        Support ISP (In-System Programmable)/IAP (In-Application Programmable), can directly download user programs through the serial port (RXD/P3.0, TXD/P3.1),

2) Data storage

        The chip integrates 256 bytes of on-chip temporary storage and 512 bytes/1K bytes of XRAM; XRAM is enabled by clearing AUXR.XRAM.

3. General I/O port

        There are five 8-bit I/O ports: P0-P4; after reset, all I/O ports are quasi-bidirectional/weakly pulled up (same as P1 port of ordinary 8051).

        All I/O ports can be configured by software to one of four operating types: quasi-bidirectional, push-pull output, input only (high impedance), open-drain output; set by registers PnM1 and PnM0.

        When a normal I/O port is powered on, it will weakly pull up and output a high level. Adding a pull-down resistor to the I/O port can make the I/O port output a low level when it is reset.

1) Quasi-bidirectional port

        When outputting 1, the driving capability is very weak, and when outputting 0, the driving capability is very strong. Before the quasi-bidirectional port reads the external state, the latch must be set to 1 in order to read the correct external state.

2) Push-pull output

        Provides a continuous strong pull-up when the latch is 1.

3) Input only (high impedance)

        The input port has a Schmitt trigger input and a interference suppression circuit.

4) Open drain output

        As a logic output, it must have an external pull-up, usually connected to VDD through a resistor. This pull-down method is the same as the quasi-bidirectional port. The open-drain port has a Schmitt trigger input and an interference suppression circuit.

 

4. Interrupt system

        The STC11/10 series provides 7 interrupt sources with 2 levels of interrupt priority, the STC12C56/STC12C54 series provides 7 interrupt sources with 4 levels of interrupt priority, and the STC12C5A series provides 10 interrupt sources with 4 levels of interrupt priority; interrupts are configured by interrupt control registers IE, IE2 and interrupt priority registers IP, IPH, IP2H.

        External interrupt 0 03H 0

 

        Timer/Counter 0 0BH 1

 

        External interrupt 1 13H 2

 

        Timer/Counter 1 1BH 3

 

        Serial port 23H 4

 

        ADC/SPI 2BH 5

 

        LVD 33H 6

 

        PCA 3BH 7        

        Serial port 2 33H 8        

        SPI 3BH 9

 

        The PCA, RXD, T1, and T0 output pins can be configured as external interrupts via the WAKE_CLK0 register.

5. Timer

        There are two 16-bit dedicated timers T0 and T1; PCA can also be used as a timer; there is also a watchdog timer;

        Timer 0 and Timer 1 are fully compatible with traditional 8051; the timer count clock source can be selected as 1/12 of the system clock or the system clock, which is set by AUXR.T0x12 and AUXR.T1x12 (when it is 0, it is the same as the traditional 51, and when it is 1, there is no frequency division).

        The watchdog is controlled by the register WDT_CONTR. Setting WDT_CONTR.CLR_WDT will restart the watchdog count.

        Watchdog overflow time = (12*division value*32768)/system clock

6.Serial port

        2 full-duplex serial ports, with the same functions as standard 51;

        Serial port 2 uses an independent baud rate generator, and serial port 1 can choose to use timer 1 or an independent baud rate generator (when AUXR.S1BRS is 0, timer 1 is used, and when it is 1, the independent baud rate generator is shared); the counting clock source of the independent baud rate generator is 1/12 of the system clock or the system clock (when AUXR.BRTx12 is 0, 1/12 of the system clock is used, and when it is 1, the system clock is used); when both serial ports use independent baud rate generators, their baud rates are the same.

        The independent baud rate generator is disabled after reset and needs to be enabled by AUXR.BRTR = 1. It has an 8-bit independent baud rate counter BRT.

        Serial port 2 baud rate calculation formula: Mode 0 baud rate = system clock/12 or system clock/2 (when AUXR.UART_M0x6 is 0, the same as standard 51)

        Mode 1, 3 baud rate = f/(256-BRT), f is the baud rate generator counter clock source frequency

        Mode 2 baud rate = 2S2SMOD*system clock/64

7. PCA (Programmable Counter Array)

        Contains an independent 16-bit timer, 2/4 16-bit capture/compare modules connected to it, each module can be programmed to work in 4 operating modes: rising/falling edge capture, software timer, high-speed output, modulated pulse output.

        The clock source of the PCA timer is set by CMOD and controlled by the PCA control register CCON.

 

       The working mode of each PCA module is set by the register CCAPMn:

1) Capture mode

       CCAPMn = 0x20 or 0x10 or 0x30,

 

       The transitions of the module's external CEXn input are sampled. When a valid transition is sampled, the PCA hardware loads the values ​​of the PCA count arrays CH, CL into the module's capture registers CCAPnH, CCAPnL.

2) Software timer mode

       CCAPMn=0X48,

 

3) High-speed output mode

       CCAPMn=0X4C,

 

4) Pulse Width Modulation (PWM) Mode

       CCAPMn = 0x42,

         Since all PCA modules share the same PCA timer, their output frequencies are the same, and the output duty cycle of each module changes independently. When the value of CL is less than (EPCnL, CCAPnL), the output is low, otherwise the output is high. The output frequency of PWM = PCA clock frequency/256.

8.A/D conversion

        There are 8-channel 10-bit high-precision ADC, the speed of which can reach 100KHZ; 8-channel voltage input A/D, which can be used for temperature detection, battery voltage detection, key scanning, and spectrum detection.

        The port to be used as A/D must be set to open-drain output or input-only mode.

        The A/D conversion is controlled by the register ADC_CONTR, and the conversion result is stored in ADC_DATA (upper 8 bits) and ADC_LOW2 (lower 2 bits)

9. EEPROM usage

        The chip integrates a data FLASH area, which can be read, written and erased through IAP.

        Related registers IAP_CONTR, IAP_CMD, IAP_TRIG, IAP_DATA, IAP_ADDRH, IAP_ADDRL

        1) Erase operation

        IAP_ADDRH = addrh;        

        IAP_ADDRL=addrl;        

        IAP_CONTR=0X81;
         IAP_CMD=0x03;
        IAP_TRIG=0X5A;
        IAP_TRIG=0XA5;        

        2) Read operation        

        IAP_ADDRH=addrh;
         IAP_ADDRL=addrl;
        IAP_CONTR=0X81;
        IAP_CMD=READ;
         IAP_TRIG=0X5A;
        IAP_TRIG=0XA5;
        _nop_();
        _nop_();
        *rdata=IAP_DATA;
        3) Write operation        

        IAP_DATA=*wdata;

        IAP_ADDRH=addrh;

        IAP_ADDRL=addrl;

        IAP_CONTR=0X81;

        IAP_CMD=WRITE;

        IAP_TRIG=0X5A;

        IAP_TRIG=0XA5;