ARM Porting BootLoader(1)

　 　The implementation of BootLoader depends on the CPU architecture, so most BootLoaders are divided into two parts: stage1 and stage2. Codes that depend on the CPU architecture, such as device initialization code, are usually placed in stage1, and are usually implemented in assembly language to achieve the purpose of being concise and powerful. Stage2 is usually implemented in C language, which can achieve more complex functions, and the code will have better readability and portability. The

　　stage1 of BootLoader usually includes the following steps:

　　· Hardware device initialization;

　　· Prepare RAM space for loading the stage2 of BootLoader;

　　· Copy the stage2 of BootLoader to the RAM space;

　　· Set up the stack;

　　· Jump to the C entry point of stage2.

　　The stage2 of BootLoader usually includes the following steps: 

　　· Initialize the hardware devices to be used in this stage;

　　· Detect the system memory map (memory map);

　　· Read the kernel image and the root file system image from the flash to the RAM space;

　　· Set the startup parameters for the kernel;

　　· Call the kernel.

　　The BootLoader in this system is modified with reference to the vivi of Mizi Company in South Korea.

　　1. Development environment

　 　We purchased the integrated software and hardware development platform ADT (ARM Development Tools) for embedded software development with independent intellectual property rights developed by Wuhan Chuangwei Information Technology Co., Ltd. It provides a complete set of development solutions for embedded applications based on ARM core, including program editing, project management and settings, program compilation, program debugging, etc. The

　　 ADT embedded development environment consists of ADT Emulator for ARM and ADT IDE for ARM. ADT Emulator for ARM implements debugging support functions between the host and the target machine through JTAG. It does not require target memory and does not occupy any port resources of the target system. The target program runs directly on the target board and is debugged through the JTAG boundary scan port of the ARM chip. It is a completely non-intrusive debugging, and its simulation effect is close to the real system.

　　ADT IDE for ARM provides users with an efficient and clear graphical embedded application software development environment, including a complete set of development and debugging tools for embedded systems: source code editor, project manager, project compiler (compiler, assembler and connector), integrated debugging environment, ADT Emulator for ARM debugging interface, etc. Its interface is similar to the Microsoft Visual Studio environment. Users can create projects, open projects, create, open and edit files, compile, connect, set up, run and debug embedded applications in the ADT IDE for ARM integrated development environment. The

　　ADT embedded software development environment adopts a host-target cross-development model. ADT IDE for ARM runs on the host side, and ADT Emulator for ARM realizes the connection between ADT IDE for ARM and the target machine. During development, ADT IDE for ARM is first used to compile and link to generate the target code, and then a debugging channel is established with ADT Emulator for ARM. After the debugging channel is successfully established, the target board can be controlled by ADT Emulator for ARM in ADT IDE for ARM to debug the target program, including downloading the target code to the target machine, controlling program execution, observing debugging information, etc.


　　2. ARM assembly

　　ARM itself belongs to the RISC instruction system, the number of instructions is very small, and its programming is mainly based on high-level languages ​​such as C. We only need to use a small number of assembly instructions in the first stage of the Bootloader:

　　(1) +- operation

ADD r0, r1, r2  ―― r0 := r1 + r2 SUB r0, r1, r2  ―― r0 := r1 - r2

　　The second operand can be an immediate value:

ADD r3, r3, #1  ―― r3 := r3 + 1

　　The second operand can also be the result of a bit shift operation:

ADD r3, r2, r1, LSL #3  ―― r3 := r2 + 8.r1

　　(2) Bit operations

AND r0, r1, r2  ―― r0 := r1 and r2 ORR r0, r1, r2 ―― r0 := r1 or r2 EOR r0, r1, r2 ―― r0 := r1 xor r2 BIC r0, r1, r2  ―― r0 := r1 and not r2

　　(3) Register transfer

MOV r0, r2  ―― r0 := r2 MVN r0, r2  ―― r0 := not r2

　　(4) Comparison

CMP r1, r2  ―― set cc on r1 - r2 CMN r1, r2  ―― set cc on r1 + r2 TST r1, r2  ―― set cc on r1 and r2 TEQ r1, r2  ―― set cc on r1 or r2

　　These instructions affect the (N, Z, C, V) bits in the CPSR register.

　　(5) Memory Operations

LDR r0, [r1]  ―― r0 := mem [r1] STR r0, [r1]  ―― mem [r1] := r0 LDR r0, [r1, #4]  ―― r0 := mem [r1+4] LDR r0, [r1, #4] !  ―― r0 := mem [r1+4] r1 := r1 + 4 LDR r0, [r1], #4 ―― r0 := mem [r1] r1 := r1 +4 LDRB r0 , [r1]  ―― r0 := mem8 [r1] LDMIA r1, {r0, r2, r5} ―― r0 := mem [r1] r2 := mem [r1+4] r5 := mem [r1+8]

　　{..} can include all registers from r0 to r15. If r15 (PC) is included, the program will jump.

　　(6) Control flow

　　Example 1:

MOV r0, #0 ; initialize counter LOOP: ADD r0, r0, #1 ; increment counter CMP r0, #10 ; compare with limit BNE LOOP ; repeat if not equal

　　Example 2:

CMP r0, #5  ADDNE r1, r1, r0  SUBNE r1, r1, r2  ―― if (r0 != 5) { r1 := r1 + r0 - r2 }