Follow me to write ARM processor part 1: start from writing module arm

I decided to share my experience of writing ARM processors with you. I am not bragging, my core is a very good core. One way to prove it is to download it into FPGA to see if it works. I have already done this method of proof. If you can download the entire project file and modify it slightly, you can verify whether it is successful. But this is not the way to promote it. Because for most people, they only know the results but not the reasons. People always feel mysterious about things they are not familiar with or do not understand, so their application will be greatly reduced. The best way to promote it is to make it a core that everyone can easily write. I hope to promote everyone's enthusiasm for SOC design. It is conceivable that if the most mysterious and complex CPU core can be easily written, then what else can be difficult for us?

 
   Before writing, I want to state two points. These two points are certainly not created by me. I just quoted them so that you can read more and believe that I can create this miracle. Of course, you can also create this miracle. The first point is the "divide and annihilate" that Chairman Mao often used in military affairs. In politics, it means "pull one faction and attack another faction". This trick has been tried and tested in Chairman Mao's struggle career and made him a great man. This point is called "divide and conqur (not spelled correctly, too lazy to check)" abroad, and it is also a very important method. So when facing a behemoth, don't be afraid, you must use this "magic weapon". The first step is to try to "divide" first, and make this behemoth smaller, and then smaller. First, analyze it in detail, which is already half successful; the second step is to start from the smallest, do it bit by bit, do it right, and do it well. How good is it? It should be so good that this small point will never disturb us from continuing to conquer the next small point. Then conquering this behemoth is just a matter of time. Including writing this article now, I have to use this spirit, otherwise, there are so many things to say, where can I start? Where can I make it clear? Don't be afraid, since I have conquered ARM core with this method, then it is definitely easier to explain it and make it clear than to write ARM core. I believe I can also complete it.
   
   But I lack something: that is the perspective problem. Because I stand on my position, I know everything. When I talk, I just take it for granted that everyone should know what I think from my perspective. But in fact, the gap in the middle is as far as the gap between dreams and reality. So I need everyone to have feedback, that point is ignored, remind me in time, let me always stand on everyone's position and talk about things, instead of letting me talk to myself. If I talk to myself, the effect is very poor. So please help me, helping me is to help myself. If possible, please raise the points you don't understand in time. Let me conquer this section today without disturbing me to conquer the next section, which is in line with my spirit above.
   
   Some netizens may ask, what am I trying to do? Why do you want to help me? What am I trying to do? Anyway, I was a naughty kid since I was young. The more adults told me not to do something, the more I was willing to take risks. Of course, generally speaking, I was obedient when I was young. I was a person who only did "constructive" destruction. I didn't do things like digging out hornets' nests and blocking chimneys. Now there is a particularly meaningful thing, such as these masters of ARM company, who are selling ARM7 cores with great pleasure. Suddenly, I broke in and said that this thing is not worth much at all, you have to sell the real thing, isn't it very interesting? The more unhappy ARM company is, the happier it is for everyone. Because everyone's overall level has improved, then ARM company must work hard to improve its own level, so as to highlight its own value. So this thing is particularly interesting when I think about it, so I decided to do such a "constructive" destructive thing. So please help me, helping others is actually also achieving yourself, please practice with me. So, if I were a software engineer, I would definitely write some viruses or something, it's interesting! But don't worry, I will only do "constructive" things, and the viruses I make will never cause too much trouble to everyone, because this does not fit my style. But now that I am a hardware engineer, I have to find ways to do something big on hardware. Do something that will make some "adults" unhappy. People are here to have fun. Haha, I've said too much.
   
   After talking for a long time, I haven't mentioned the second point. In fact, the second point is also included in the first point. But there is still a difference. The second point is the ancient people's effort to "investigate things and gain knowledge". In ancient times, these Confucian scholars often spent a long time investigating a flower or a leaf, which is the ultimate of this spirit. "Divide and conqur" is just a principle of struggle, but how to conqur? I think we should use the ancient people's "investigate things and gain knowledge", that is, be patient and "conqur" from the smallest things. I will describe each net and each wire later, which is the result of "conqur". The CPU is a complex system. To do it well, you have to use nets, wires, and registers to build it. I heard that Intel does this. But I am different from it. Because my system still leaves a lot of work to the synthesizer to complete, I just describe it so that the synthesizer can understand it.
   
   Without further ado, I hope that after reading this series of articles, you will be able to write my arm core. Of course, you can give it your best, but I hope that you can give it your best and write this core better. Because I am doing something unorthodox, how can I expect others to "stick to the rules" and take my core as a benchmark? I just hope to throw out a brick to inspire others. I want to throw out a brick and say to the emperor's new clothes of arm: You are not wearing any clothes at all! Don't I know this, shouldn't I tell everyone? So feel free to waste my arm core, because in this way, its existence has a greater meaning. I
   
   started writing: The first sentence is: module arm (. This is probably the classic opening of Verilog design. Then what? It is to define the interface. The interface actually specifies most of the functions. For the reuse of IP cores, it is necessary to explain the interface clearly and to the next party clearly so that others can use the core.

    module arm (
                 clk,
                 rst,
                 cpu_en,
  clk is the clock, rst is the asynchronous reset signal. I don't need to explain this. What is cpu_en? cpu_en is a synchronous enable signal. That is to say, only when cpu_en==1'b1, the entire core will work. If cpu_en==1'b0, then this arm The core will not work. Simply put, all registers in this Verilog file will not be changed. This is like the "time stop" mentioned in some fairy tales. The people in the castle are quiet and everything stops. Then the registers belong to the people living in the castle, because as long as they are quiet, there are no living things, and the tools that rely on people will not move. This cpu_en is also important for the entire module. For example, if you don't want it to work, you can set cpu_en==1'b0, then it will not work. To make it work again, just set "cpu_en==1'b1". In this FPGA project, I used this input to connect to a "switch". If it is turned to "1'b1", the system starts to work; if it is turned to "1'b0", it stops, and I will download the new code to its ROM through the serial port.

                cpu_restart,
                irq,
                fiq,
                rom_abort,
                ram_abort,
 these are the five interrupt sources of ARM. For details, please refer to the ARM documentation. I will just briefly introduce them here. cpu_restart is equivalent to a synchronous reset. As long as it is high level, the system will start again. irq and fiq are two interrupts. As long as it is equal to "1'b1", if cpsr does not turn it off, the corresponding interrupt must be executed. rom_abort and ram_abort correspond to rom and ram read errors, and an interrupt is started to handle these things.

               The three signals rom_en,
               rom_addr, and
               rom_data
  are connected to the ROM and are the source of instructions. The method of fetching instructions is: when rom_en==1'b1, the code stored in the rom_addr position will appear in rom_data at the next clock. Of course, if rom_en==1'b0, rom_data will keep its original value unchanged. This is a very ordinary ROM. The initiative of fetching instructions is in the hands of the ARM core. What if it has to process very complex instructions and cannot handle them in one cycle? Then do not start rom_en. Only when the processing is completed and there is free time, start rom_en and update rom_data.

               ram_cen,
               ram_wen,
               ram_addr,
               ram_wdata,
               ram_rdata,
               ram_flag
              );
  The first five "ram_cen, ram_wen, ram_addr, ram_wdata, ram_rdata" are typical single-port RAM interfaces. The function is: when ram_cen==1'b1, start to perform operations on RAM, and at the same time ram_wen==1'b1, perform write operations and write ram_wdata to the corresponding position of ram_addr; if ram_wen==1'b0, it means it is a read operation, and the data in ram_addr must appear in ram_rdata at the next clock.
  ram_flag is a new addition by me. Because LDRB and STRH appear in RAM for byte and word operations. In order to simplify the operation, I give each byte a corresponding flag bit: if ram_flag[0]==1'b1, it means the operation of the first byte is valid; if ram_flag[0]==1'b1, the read and write operations are invalid for the first byte. For example, if I execute STRB 0x4000_0000, ram_flag==4'b0001, which means only the lower 8 bits of address 0x4000_0000 are written. If STRH 0x4000_0002, ram_flag==4'b1100, which means writing the upper 2 bytes of 0x4000_0000.
   So I suggest connecting 4 RAMs, each with a width of 8 bits. Let the ARM core operate on each byte independently. Then the cen of each block is: ram_cen&ram_flag[3]; ram_cen&ram_flag[2]; ram_cen&ram_flag[1]; ram_cen&ram_flag[0].

   OK, next, here are the definitions of their bit widths:
    input clk;
    input rst;
    input cpu_en;

    input cpu_restart;
    input irq;
    input fiq;
    input rom_abort;
    input ram_abort;

    output rom_en;
    output [31:0] rom_addr;
    input [31:0] rom_data;

    output ram_cen;
    output ram_wen;
    output [31:0] ram_addr;
    output [31:0] ram_wdata;
    input [31:0] ram_rdata;
    output [31:0] ram_flag;

  Okay, that’s the end of this article, see you in the next section!