ARM assembly language series based on Android: ARM assembly language introduction

Part 1: Introduction to ARM assembly language 
Part 2: Analysis of the process of generating ARM assembly programs from C/C++ programs Part 
3: ARM assembly language program structure 
Part 4: Addressing methods of ARM processors 
Part 5: ARM instruction set and Thumb instruction set 
Part 6: NEON instruction set and VFP instruction set

This is the opening article of the blog. Here I will first introduce the general classification and functions of ARM processors.

1. ARM processor and ARM instruction set

The entire ARM processor is divided into three parts:

• Classic
• Embedded
• Application

Classic is called the classic series.

ARM1~ARM11 have always been named with numbers, and ARM12 and later have been named Cortex. Cortex has the following categories:

• Cortex-A: Widely used in smartphones, netbooks, e-books, and digital TVs.
• Cortex-M: Used in the field of microcontrollers, this series is characterized by high energy efficiency and low power consumption.
• Cortex-R: Used to support deeply embedded real-time applications, this series is characterized by low power consumption, good interrupt behavior, excellent performance and high compatibility with existing platforms.

Although there are many versions of ARM processors, many models of ARM processors are compatible with a set of ARM instruction sets. The corresponding relationship between ARM architecture and ARM processors is shown in the following figure:

The technologies involved in the above figure are briefly mentioned here:

• VFP: Provides floating-point arithmetic capabilities for ARM processors.
• Jazelle: Allows accelerated execution of Java bytecode on certain hardware architectures.
• SIMD: SIMD instruction set.
• TrustZone: Security control to protect products from external malicious attacks.
• NEON: NEON is an extension of the SIMD architecture. NEON takes fewer instruction cycles to execute than traditional SIMD.

Android initially chose ARM as the processor architecture for platform devices and made special optimizations. After the development of Android 4.1, it has fully supported processors of three architectures: ARM, x86 and MIPS.

2. Working mode and working status of ARM processor

2.1 ARM processor working mode

The ARM processor has a total of 37 32-bit processors, including 31 general registers and 6 status registers. The ARM processor supports 7 operating modes, namely:

• User mode (usr): The normal program running state of the ARM processor.
• Fast interrupt mode (FLQ): used for high-speed data transmission or channel processing.
• External interrupt mode (irq): used for general interrupt processing.
• Supervisor mode (svc): The protection mode used by the operating system.
• Data access termination mode (abt): This mode is entered when data or instruction prefetching is terminated and can be used for virtual storage and storage protection.
• System mode (sys): runs very short-lived operating system tasks.
• Undefined instruction termination mode (und): This mode is entered when an undefined instruction is executed.

2.2 Working status of ARM processor

• ARM state: Execute 32-bit word-aligned ARM instructions.
• Thumb state: executes 16-bit word-aligned ARM instructions.

The naming of registers in Thumb state is slightly different from that in ARM. Their corresponding relationships are as follows:

• R0~R7 in Thumb state are the same as R0~R7 in ARM state.
• The CPSR in Thumb state is the same as the CPSR in ARM state.
• FP in Thumb state is the same as R11 in ARM state.
• IP in Thumb state is the same as R12 in ARM state.
• SP in Thumb state is the same as R13 in ARM state.
• LR in Thumb state is the same as R14 in ARM state.
• The PC in Thumb state is the same as R15 in ARM state.