ARM processor modes and on-chip registers, ARM exceptions and interrupts

 

There are two ways to switch the working mode of Arm:

Passive switching: some exceptions or interrupts are generated when the arm is running to automatically switch modes

Active switching: through software changes, that is, the software sets the register to perform arm mode switching, because the arm's working mode can be switched by assigning values ​​to the corresponding registers.

Tips: When the processor runs in user mode, certain protected system resources cannot be accessed.

Except for the user mode, the other six working modes are privileged modes;

The other five modes in the privileged mode except the system mode are called exception modes;

Most programs run in user mode;

Entering privileged mode is to handle interrupts, exceptions, or access protected system resources;

4. Register

ARM has 31 general 32-bit registers and 6 program status registers, which are divided into 7 groups. Some registers are shared by all working modes, and some registers are specific to each working mode.

R13 - Stack pointer register, used to save the stack pointer;

R14 - Program connection register. When the BL subroutine call instruction is executed, R14 gets the backup of R15. When an interrupt or exception occurs, R14 saves the return value of R15.

R15——Program counter;

The fast interrupt mode has 7 backup registers R8-R14, which makes it unnecessary to save any registers when entering the fast interrupt mode to execute a large part of the program;

Other privileged modes have two independent copies of registers, R13 and R14, so that each mode can have its own stack pointer and connection registers;

5. Current Program Status Register (CPSR)

The meaning of each bit in CPSR is as follows:

T bit: 1——CPU is in Thumb state, 0——CPU is in ARM state;

I, F (interrupt disable bit): 1-disable interrupt, 0-enable interrupt;

Working mode bits: These bits can be changed to switch modes;

6. Program Status Save Register (SPSR)

When switching to a privileged mode, the SPSR saves the CPSR value of the previous working mode, so that when returning to the previous working mode, the value of the SPSR can be restored to the CPSR;

7. Mode Switching

When an exception occurs and the CPU enters the corresponding exception mode, the following tasks are automatically completed by the CPU:

1. Save the address of the next instruction to be executed in the previous working mode in R14 of the exception mode;

2. The value of CPSR is transferred to the SPSR of the abnormal mode;

3. Set the working mode of CPSR to the working mode corresponding to the abnormal mode;

4. Set the PC value to the address of this exception mode in the exception vector table, that is, jump to execute the corresponding instruction in the exception vector table;

When returning from an abnormal working mode to the previous working mode, the software needs to complete the following tasks:

1. Subtract an appropriate value (4 or 8) from R14 in the exception mode and assign it to the PC register;

2. Assign the value of the exception mode SPSR to the CPSR;

ARM has seven exceptions. When an exception occurs, the ARM core will automatically execute the instructions in the Vector Table.

ARM's seven exceptions and their offsets in the Vector Table:   

The address of the Vector Table of ARM versions below V4 is 0x00000000. The address of the Vector Table of versions above V4 can be selected between 0x00000000 and 0xFFFF0000.

In the ARM architecture, interrupts are a type of exception. Taking interrupts as an example, when an interrupt is received, the ARM core first saves the CPSR and PC registers in the current mode to the SPSR and LR registers in the exception mode, and then sets the PC register value of the target mode to address 0x00000018 (or 0xFFFF0018), and finally switches to the target mode, that is, the IRQ mode. The first instruction executed after switching to the target mode is the instruction at address 0x00000018 (or 0xFFFF0018). This is generally a jump instruction, which is used to jump to the interrupt processing function. Other exception handling methods are similar.

S3C6410 has a 32KB IROM (internel ROM) with a program embedded in it. The beginning of the program is a Vector Table. When booting in IROM mode, IROM is mapped to 0x00000000, so the first instruction executed is the Reset exception jump instruction in the Vector Table (the first instruction is taken at address 0 when the ARM core is powered on). We can use the exception vector table of this IROM to implement interrupt processing under u-boot.

Just after power-on, the interrupt is initialized so that S3C6410 can receive and process interrupts. After an interrupt occurs, the exception jump in 0x00000018 is executed first, and then the interrupt processing function in IROM is executed. This processing function is very simple: the value at 0x0C001FF8 (which falls within the SRAM address range) is assigned to PC. Therefore, we can store the entry address of our own interrupt processing function at 0x0C001FF8, and when an interrupt occurs, our interrupt processing function will be automatically called. The implementation method of other exceptions is similar, except that 0x0C001FF8 needs to be changed to another value. The specific value needs to be analyzed in the code in IROM.

The disassembled code of S3C6410 IROM can be searched on the Internet, or you can extract and disassemble it yourself.