ARM instruction set and common registers-EEWORLD

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1) ARM instruction set 32-bit ARM instructions and 16-bit Thumb instructions

1. Register addressing

MOV R1, R2 //Transfer the value of register R2 to register R1

2. Immediate addressing

MOV R0, #0XFF00 //Data is included in the instruction

3. Register offset addressing

MOV R0, R2, LSL #3 //The value of R2 is shifted left by 3 bits, and the result is placed in R0, that is, R0 = R2 * 8

LSL logical left shift, LSR logical right shift, ASL arithmetic left shift, ASR arithmetic right shift, ROR circular right shift, RRX circular right shift with extension

4. Register indirect addressing

LDR R1, [R2] //Use the value in R2 as the address, retrieve the data at this address and save it in R1

SWP R1, R1, [R2] //Use the value in R2 as the address

5. Base addressing adds the contents of the base register to the offset given in the instruction to form an effective address

LDR R2, [R3, #0x0F] // Add 0x0F to the value in R3 as the address, and save the data in R2

LDR R0, [R1], #-4 //Store the content of address R1 into R0, and R1 = R1 - 4

STR R1, [R0, #-2] // Subtract 2 from the value in R0 and use it as the address.

6. Multi-register addressing

LDMIA R1!, {R2-R7, R12} //Read the data of R1 unit into R2-R7, R12, R1 automatically increases by 1

STMIA R0!, {R3-R6, R10} //Save the data in R3-R6 to the address pointed to by R0, and R0 will automatically increase by 1

7. Stack addressing

Fully increasing LDMFA STMFA

Full Decrement LDMFD STMFD

Empty increment LDMEA STMEA

Empty decrement LDMED STMED

8. Block copy addressing multi-register transfer instructions are used to copy a block of data from one location in the memory to another location.

STMIA R0!, {R1-R7}

STMIB R0!, {R1-R7}

STMDA

STMDB

9. Relative addressing

The program counter PC provides the base address, and the address code field in the instruction is used as the offset. The address obtained by adding the two is the effective address of the operand.

The ones with S will affect the CPSR register and the flag bit

R15 is the program counter PC.

2) ARM memory access instructions

The ARM processor is a typical RISC processor with a load/store architecture. Access to memory can only be achieved using load and store instructions. LDR/STR

Batch load and store instructions can load/store the contents of multiple registers with one instruction, greatly improving efficiency.

Content exchange instructions can be used for semaphore operations, etc. The ARM processor is a von Neumann storage structure, with unified addressing of program space, RAM space and IO mapping space.

In addition to RAM operations, access to peripheral IO and program data must be performed through load/store instructions.

LDR/STR T is an optional suffix. T indicates that the processor is in privileged mode. The suffix ! indicates that the result is written back. S indicates sign extension.

The B suffix represents one byte, and the H represents a half word (2 bytes).

Program relative offset LDR Rd, label; //label is the program label, which must be within the range of +-4KB of the current instruction

1. LDM and STM can realize data transmission between a group of registers and a continuous memory unit. It is mainly used for field protection, data, parameter transfer, etc.

IA: Address plus 4 after transmission DA: Address minus 4 after transmission

IB Add 4 to the address before transmission DB Subtract 4 from the address before transmission

STMFD R0!, {R0-R7, LR} //Save on-site and push R0-R7, LR into the stack

LDMFD R1!, {R0-R7, PC} //Restore the scene exception handling return

2. SWP

Register and memory exchange instruction, used to read the contents of a memory cell (the cell address is placed in register Rn) into a register Rd, and at the same time

The contents of a register Rm are written to this memory cell.

SWP R1, R2, [R0] //Read a byte from the storage unit pointed to by R0 into R1 (clear the upper 24 bits), and write the content of R2 into the memory unit

3) ARM jump instruction

B label jump instruction Pc<-label is limited to the range of +-32KB of the current instruction

BL label Jump instruction with link LR<- PC-4, PC<- label is used for subroutine call

BX Rm Jump instruction with state switching PC<- label switching state

4) ARM coprocessor instructions

1. CDP notifies the ARM coprocessor to perform specific operations

2. LDC reads data from a continuous memory unit into the coprocessor register

LDC p5, c2, [R2, #4] //Read the data pointed to by R2+4 in the memory unit and transfer it to the c2 register of coprocessor p5

3. STC writes the coprocessor register data to a continuous memory unit

4. MCR transfers the data in the ARM processor's register to the coprocessor's register.

5. MRC transfers the data in the coprocessor's register to the ARM processor's register.

5) ARM miscellaneous instructions

SWI immediately——24 soft interrupt instruction processor enters management mode

MRS Rd, psr Read Status Register Instruction

MSR psr_fields, Rd/#immed_8r Write Status Register Instruction

6) ARM pseudo-instructions

The ADR pseudo-instruction is a small-range address read pseudo-instruction used to read the address value of the PC relative offset into a register.

The medium-range address read pseudo-instruction in the ADRL pseudo-instruction is used to read the address value of the PC relative offset or the address value based on the register relative offset into the register.

The LDR pseudo-instruction is a large-range address read pseudo-instruction used to load a 32-bit immediate value or an address into a specified register.

NOP pseudo instruction No operation pseudo instruction

The ARM assembler consists of machine instructions, pseudo-instructions, and macro-instructions. Pseudo-instructions are not executed by the machine during the processor operation like machine instructions, but by the assembler.

Processing of source program.

1) Symbol definition directive

GBLA global arithmetic variables are initialized to 0 LCLA local SETA assignment

GBLL global logical variable initialized to false LCLL local SETL assignment

GBLS global string variable initialized to empty LCLS local SETS assignment

The ARM processor has a total of 37 registers. These include:

** 31 general purpose registers, including the program counter (PC). These registers are 32-bit registers.

** 6 status registers. These registers are also 32-bit registers.

ARM processors have 7 different processor modes, each of which has a corresponding register set. At any time, the visible registers include 15 general registers

(R0-R14), one or two status registers and the program counter (PC). Among all the registers, some share a physical register for each mode, and some store

Each mode has its own independent physical registers.

*************************************************** **

General registers ARM

General registers are divided into the following three categories: backup registers, unbacked registers, and program counter PC

Backup register

For R8-R12 backup registers, each register corresponds to two different physical registers. The system does not use the backup registers for any special purpose, but

When interrupt handling is very simple and only uses registers R8-R14, the FIQ handler does not need to execute instructions to save and restore the interrupt context, thus making the interrupt handler

Interrupt processing is very fast. ARM

For R13 and R14 backup registers, each register corresponds to six different physical registers, one of which is shared by system mode and user mode;

The five corresponding to the other five processor modes. The following notations are used to distinguish the physical registers:

R13_ string 5

MODE can be one of the following modes: usr,svc,abt,und,irq,fiq

String 5

Registers not backed up

The unbacked registers include R0-R7. For each unbacked register, the same physical register is used in all processor modes.

Unbacked registers are not used by the system for special purposes and can be used wherever general-purpose registers can be used.

Program Counter PC

It can be used as a general register, but some instructions have some restrictions when using R15. Because ARM uses a pipeline processor mechanism, when it is correctly read

When the PC value is set, the value is the current instruction address plus 8 bytes. In other words, for the ARM instruction set, PC points to the address of the next two instructions of the current instruction.

Since ARM instructions are word-aligned, the 0th and 1st bits of the PC value are always 0.

It should be noted that when using str/stm to save R15, it may save the current instruction address value plus 8 bytes, or it may save the current instruction address value plus 12.

Bytes. Which method is used depends on the specific design of the chip. For users, try to avoid using STR/STM instructions to save the value of R15.

When a value is successfully written to R15, the program will jump to that address for execution. Since ARM instructions are word-aligned, the value written to R15 should satisfy bits [1:0] 0b00

, the specific requirements for arm versions are different:

**For arm3 and lower versions, the address value bits[1:0] written to R15 are ignored, that is, the address value written to r15 will be ANDed with 0xFFFF FFFC.

**For ARM4 and higher versions, the program must ensure that the address value bits[1:0] written to R15 is 0b00, otherwise unpredictable consequences will occur.

For the Thumb instruction set, instructions are aligned and the processor will ignore bit[0].

Reference address：ARM instruction set and common registers

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