Detailed explanation of Uboot transplantation on S3C2440 (Part 1)

#gedit Makefile

CROSS_COMPILE ?= arm-linux- //Specify the cross compiler as arm-linux-gcc

smdk2410_config : unconfig //2410 compilation option format
@$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 samsung s3c24x0

my2440_config : unconfig //2440 compilation option format
@$(MKCONFIG) $(@:_config=) arm arm920t my2440 samsung s3c24x0

*Description: arm: CPU architecture (ARCH)

arm920t: CPU type

my2440: corresponds to the directory where a new development board project is created under the board directory

samsung: The parent directory of the new development board project directory. If you create a new development board project directory directly under board, this will be NULL

s3c24x0: CPU model

*Note: The second line of the compilation option format must start with the Tab key, otherwise the compilation will fail.

#make my2440_config //If Configuring for my2440 board... appears, the settings are correct

#make //After compiling, the u-boot.bin file will appear in the root directory, and the first step of u-boot transplantation is completed

/*
* the actual start code
*/

start_code:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0

bl coloured_LED_init //The two lines here are to initialize the LED on the AT91RM9200DK development board
bl red_LED_on

/*bl coloured_LED_init//These two lines are the LED initialization of the AT91RM9200DK development board, comment out
bl red_LED_on*/

#if defined(CONFIG_S3C2440) //Different from other development boards

//According to the mini2440 schematic diagram, the LEDs are controlled by ports PB5, 6, 7, and 8 of the S3C2440. The following are the base addresses of the PB port registers (check the DataSheet of 2440)
#define GPBCON 0x56000010
#define GPBDAT 0x56000014
#define GPBUP 0x56000018

//The following register operations refer to the S3C2440 DataSheet
ldr r0,=GPBUP
ldr r1,=0x7FF //That is: binary 11111111111, turn off the PB port pull-up
str r1,[r0]

ldr r0,=GPBCON //Configure PB5, 6, 7, 8 as output ports, corresponding to bits 10-17 of the PBCON register
ldr r1,=0x154FD //That is: binary 010101010011111101
str r1,[r0]

ldr r0,=GPBDAT
ldr r1,=0x1C0 //That is: binary 111000000, PB5 is set to low level, 6, 7, 8 are high level
str r1,[r0]

#endif

//This code turns on LED1 on the development board after u-boot is started, while LED2, LED3, and LED4 are off

#gedit include/configs/my2440.h

#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */
#define CONFIG_S3C2440 1/* in a SAMSUNG S3 C2440 SoC */

#gedit board/samsung/my2440/my2440.c //Set the main frequency and USB clock frequency parameters to be consistent with those in start.S

#define FCLK_SPEED 2 //The default setting is 2, which means the red code below is valid

#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
#define M_MDIV 0xC3
#define M_PDIV 0x4
#define M_SDIV 0x1
#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
#define M_MDIV 0xA1
#define M_PDIV 0x3
#define M_SDIV 0x1
#elifFCLK_SPEED==2/* Fout = 405MHz */
#defineM_MDIV 0x7F //These three values ​​are set according to the "PLL VALUE SELECTION TABLE" section of the S3C2440 chip manual
#define M_PDIV 0x2
#define M_SDIV 0x1
#endif

#define USB_CLOCK 2 //The default setting is 2, which means the red code below is valid

#if USB_CLOCK==0
#define U_M_MDIV 0xA1
#define U_M_PDIV 0x3
#define U_M_SDIV 0x1
#elifUSB_CLOCK==1
#define U_M_MDIV 0x48
#define U_M_PDIV 0x3
#define U_M_SDIV 0x2
#elifUSB_CLOCK==2/* Fout = 48MHz */
#defineU_M_MDIV 0x38 //These three values ​​are set according to the "PLL VALUE SELECTION TABLE" section of the S3C2440 chip manual
#define U_M_PDIV 0x2
#define U_M_SDIV 0x2
#endif

#gedit cpu/arm920t/start.S

#if defined(CONFIG_S3C2400)|| defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
/* turn off the watchdog */

# if defined(CONFIG_S3C2400)
# define pWTCON 0x15300000
# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
# define CLKDIVN 0x14800014 /* clock divisor register */
#else //The register addresses of 2410 and 2440 below are consistent
# define pWTCON 0x53000000
# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
# define INTSUBMSK 0x4A00001C
# define CLKDIVN 0x4C000014 /* clock divisor register */
# endif

ldr r0,=pWTCON
mov r1, #0x0
str r1,[r0]

/*
*mask all IRQs by setting all bits in the INTMR - default
*/
mov r1, #0xffffffff
ldr r0,=INTMSK
str r1,[r0]
# if defined(CONFIG_S3C2410)
ldr r1,=0x3ff
ldr r0,=INTSUBMSK
str r1,[r0]
# endif
# if defined(CONFIG_S3C2440)//Add interrupt disable part of s3c2440
ldr r1,=0x7fff //According to the 2440 chip manual, the INTSUBMSK register has 15 bits available

ldr r0,=INTSUBMSK
str r1,[r0]
# endif

# if defined(CONFIG_S3C2440) //Add the clock part of s3c2440# endif
#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 || CONFIG_S3C2440 */

#define MPLLCON 0x4C000004 //System main frequency configuration register base address

#define UPLLCON 0x4C000008 //USB clock frequency configuration register base address
ldr r0,=CLKDIVN //Set the frequency division coefficient FCLK:HCLK:PCLK = 1:4:8
mov r1,#5
str r1,[r0]

ldr r0, =MPLLCON //Set the system main frequency to 405MHz

ldr r1, =0x7F021 //This value refers to the "PLL VALUE SELECTION TABLE" section of the chip manual

str r1, [r0]

ldr r0, =UPLLCON //Set USB clock frequency to 48MHz

ldr r1, =0x38022 //This value refers to the "PLL VALUE SELECTION TABLE" section of the chip manual

str r1, [r0]

#else //The clock part of other development boards, don't worry about it here, we are now working on 2440

/* FCLK:HCLK:PCLK = 1:2:4 */
/* default FCLK is 120 MHz !*/

ldr r0,=CLKDIVN
mov r1, #3
str r1,[r0]

#gedit cpu/arm920t/s3c24x0/speed.c //Modify the function of obtaining the clock frequency according to the set frequency division coefficient FCLK:HCLK:PCLK = 1:4:8

static ulong get_PLLCLK(int pllreg)
{
S3C24X0_CLOCK_POWER *const clk_power =S3C24X0_GetBase_CLOCK_POWER();
ulong r, m, p, s;

if(pllreg == MPLL)
r = clk_power->MPLLCON;
elseif(pllreg == UPLL)
r = clk_power->UPLLCON;
else
hang();

m =((r & 0xFF000)>> 12)+ 8;
p =((r & 0x003F0)>> 4)+ 2;
s = r & 0x3;

#if defined(CONFIG_S3C2440)
if(pllreg == MPLL)
{ //Refer to the formula in the S3C2440 chip manual: PLL=(2 * m * Fin)/(p * 2s)
return((CONFIG_SYS_CLK_FREQ * m * 2)/(p << s));
}
#endif

return((CONFIG_SYS_CLK_FREQ * m)/(p << s));
}

/* return HCLK frequency */
ulong get_HCLK(void)
{
S3C24X0_CLOCK_POWER *const clk_power =S3C24X0_GetBase_CLOCK_POWER();

#if defined(CONFIG_S3C2440)
return(get_FCLK()/4);
#endif

return((clk_power->CLKDIVN & 0x2)? get_FCLK()/2 : get_FCLK());
}

/*#ifndef CONFIG_SKIP_LOWLEVEL_INIT //Shield u-boot from initializing CPU and RAM in the start.S file
bl cpu_init_crit
#endif*/

#make my2440_config

#make

#gedit cpu/arm920t/start.S

.globl _start
_start: b start_code // Jump the program execution to start_code

#gedit cpu/arm920t/u-boot.lds

OUTPUT_FORMAT("elf32-littlearm","elf32-littlearm","elf32-littlearm")
OUTPUT_ARCH(arm)//Define the target platform of the generated file is arm
ENTRY(_start)//Define the entry point of the program is _start

SECTIONS
{
//Some other code segments, data segments, etc. are allocated
. = 0x00000000;

. = ALIGN(4);
.text :
{
cpu/arm920t/start.o (.text)
*(.text)
}
.............................
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}