ARM-Linux s3c2440 interrupt analysis (I)

S3C2440 is an arm920T architecture. Let’s first review the interrupt controller principles and related hardware architecture in s3c2440.

Interrupt Controller:

The interrupt controller of S3c2440A has 60 interrupt sources, such as DMA interrupt, UART interrupt, IIC interrupt, etc. The 60 interrupt sources are represented by corresponding bits in the register. When multiple interrupt requests arrive, after the arbitration process, the interrupt controller requests FIQ or IRQ interrupts from the CPU. The arbitration process is determined by the priority module in the hardware, and the result is finally written into the interrupt pending register. The value of the interrupt pending register can clearly show which interrupt has occurred.

S3c2440 interrupt controller flow chart:

Suspend

Interrupt Mode:

There are two types of interrupt modes in ARM920T (CPU): FIQ interrupt and IRQ interrupt. The former is commonly known as fast interrupt, and the latter is called normal interrupt. All interrupt sources can specify which interrupt mode to adopt. The program status register (PSR) has F and I flags. When the F bit is 1, the CPU does not accept FIQ interrupts. Similarly, when the I bit is 1, the CPU does not accept IRQ interrupts. Therefore, the interrupt controller needs to clear the F bit and the I bit, and clear the interrupt mask register (INTMSK) before receiving interrupts.

Interrupt Pending Register

S3C2440A has two interrupt pending registers: interrupt source pending register (SRCPND) and interrupt pending register (INTPND). These two registers indicate whether an interrupt is pending (generated). When an interrupt source (one or more occurring at the same time) requires an interrupt service routine, the corresponding position in the SRCPND register is set to 1, and automatically, only 1 bit in the INTPND register is set to 1 (because it can be seen from the above figure that INTPND is after the arbitration process, so the highest priority interrupt is set to 1 according to the priority). If the corresponding interrupt in INTMSK is set to 1, then the corresponding bit in SRCPND will be set to 1, and INTPND will not change. When INTPND is set, whenever the I or flag bit is 0, the interrupt service routine can be executed. The SRCPND and INTPND registers are readable and writable, so after the interrupt service routine is executed, the corresponding bit 1 should be written to the SRCPND register first, and then the corresponding bit 1 should be written to the INTPND register to complete the clearing, so that the CPU can respond to the next interrupt.

Interrupt Mask Register

The interrupt mask register INTMSK is used to indicate whether the interrupt is disabled (masked). If the corresponding position is set to 1, it indicates that the interrupt source is masked. If it is set to 0, the interrupt can be serviced normally. If an interrupt MASK is 1 and an interrupt occurs, the corresponding bit in SRCPND will be set to 1.

Interrupt Priority Generating Block

This module can service 32 interrupt requests and consists of two levels of arbitration units. The first level has 6 arbiters 0 to 5, and the second level is arbiter 6. The priority of the interrupts in each arbiter is changed by a rotation mechanism.

Each arbitrator handles 6 interrupt requests, and the rules are determined by the corresponding ARB_MODE (1 bit) and ARB_SEL (2 bits) in the priority register (PRIORTY). In the arbitrator, REQ0 is always the highest priority, and REQ5 is always the lowest. Therefore, the priority can only be set in REQ1~REQ4:

When ARB_SEL bit is 00b, priority level: REQ0, REQ1, REQ2, REQ3, REQ4, REQ5

When ARB_SEL bit is 01b, priority: REQ0, REQ2, REQ3, REQ4, REQ1, REQ5

When the ARB_SEL bit is 10b, the priority is: REQ0, REQ3, REQ4, REQ1, REQ2, REQ5

When the ARB_SEL bit is 11b, the priority is: REQ0, REQ4, REQ1, REQ2, REQ3, REQ3

The so-called priority adopts a rotation mechanism. For example, when REQ1 occurs, ARB_SEL automatically becomes 01b, so the subsequent priorities will be: REQ0, REQ2, REQ3, REQ3, REQ1, REQ5. It can be seen that when an interrupt occurs (REQ1~REQ4), its priority will be the lowest (before REQ5), and it will continue to cycle. Similarly, when REQ2 occurs, ARB_SEL automatically becomes 10b, and the subsequent priorities will be: REQ0, REQ3, REQ4, REQ1, REQ2, REQ5. But when REQ0 or REQ5 occurs, ARB_SEL will remain unchanged.

The above is when ARB_MODE is 1. When ARB_MODE is set to 0, the default mode is as shown in the figure above.

About external interrupts:

      The s3c2440 has 24 GPIO inputs to trigger external interrupts, which can be divided into low level trigger, high level trigger, falling edge trigger, rising edge trigger, or falling, rising trigger mode.

       Through the above, the interrupt controller principle and hardware architecture of s3c2440 have been analyzed. Later, the software implementation principle of interrupt analysis of ARM-Linux s3c2440 will be analyzed.