s3c6410 hardware WATCHDOG TIMER watchdog timer

  First, let's briefly describe the working process of the watchdog. The watchdog is actually a timer with a counter inside. Every time a clock signal arrives, the counter register decreases by one. If it decreases to 0, the system will restart; if the system sets the counter to a larger value before it decreases to 0, the system will not restart. When the system is normal, it will not restart; when the system fails, the count register cannot be set and the system restarts.

1. OVERVIEW Overview

The 6410 RISC microprocessor watchdog timer is used to resume the controller operation whenever it is disturbed by malfunctions such as noise and system errors. The watchdog timer generates the reset signal. It can beused as a normal 16-bit interval timer to request interrupt service.Advantage in using WDT instead of PWM timer is that WDT generates the reset signal.

The watchdog timer of the S3C6410 RISC microprocessor restores the operation of the controller when the operation is interrupted by a fault such as noise or system error. It can generate a reset signal. It can be used with a 16-bit interval timer to request interrupt service. The advantage of using a WDT instead of a PWM timer is that the WDT generates a reset signal.

2. FEATURES

The Watchdog Timer includes the following features:
• Normal interval timer mode with interrupt request.
• Internal reset signal is activated when the timer count value reaches 0 (time-out).

When the timer count reaches 0 (timeout), the internal reset signal is valid.
• Level-triggered Interrupt mechanism.

3. FUNCTIONAL DESCRIPTION

3.1. WATCHDOG TIMER OPERATION

 

 

 

The watchdog timer uses only PCLK as its source clock. The prescaler value and the frequency division factor are specified in the watchdog timer control (WTCON) register. Valid prescaler values range from 0 to 28-1. The frequency division factor can be selected as 16, 32, 64,or 128.

Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock cycle:

t_watchdog = 1/( PCLK / (Prescaler value + 1) / Division_factor )

The watchdog timer uses PCLK as the clock source, and passes through an 8-bit prescaler. The prescaler coefficient is determined by the (8~15) bits of the WTCON register. The divided frequency is equivalent to PCLK/(WTCON[8-15]+1). Then, it passes through a 4-way prescaler, and the prescaler coefficients are 16, 32, 64, and 128 respectively. It is controlled by the WTCON[4-3] bits.

If the second bit of the WTCON control register is 1, an interrupt signal is issued; if the 0th bit is 1, a reset signal is issued.

3.2、WTDAT & WTCNT

Once the watchdog timer is enabled, the value of watchdog timer data (WTDAT) register cannot be automatically reloaded into the timer counter (WTCNT). For this reason, an initial value must be written to the watchdog timer count (WTCNT) register, before the watchdog timer starts.

Once the watchdog timer is enabled, the value of the watchdog timer data (WTDAT) register cannot be automatically reloaded into the timer count (WTCNT). Before the watchdog timer starts, an initial value must be written to the watchdog timer count (WTDAT) register.

3.3、CONSIDERATION OF DEBUGGING ENVIRONMENT

When the 6410 is in debug mode using Embedded ICE, the watchdog timer must not operate.

When the S3C6410 is in debug mode (using embedded ICE), the watchdog timer cannot operate.

4. Register:

 

 

(1) The WTCON register allows the user to enable/disable the watchdog timer, select the clock signal from four different clock sources, and enable/disable the watchdog timer output.

(2) The WTDAT register is used to specify the timeout period. When the watchdog is used as a timer, when the value of the counter WTCNT reaches 0, the value of the WTDAT register will be automatically loaded into WTCNT, and no reset signal will be issued.

(3) Under normal operation, the WTCNT register contains the current count value of the watchdog timer.

(4) The WTCLRINT register is used to clear interrupts. After the interrupt service is completed, the interrupt service routine clears the related interrupts.

Note: As far as I understand, the watchdog timer actually contains two functions, one is the watchdog and the other is the timer.

When it is not used for system reset and only used for timer function, its WTDAT register is useful.

When it is used as a watchdog, the WTDAT register is meaningless. Think about it, when the watchdog cannot be fed and the system is reset, do the previously set parameters still have meaning? Therefore, only when it is used as a timer, after an interrupt occurs, the value of the WTDAT register is automatically loaded into WTCNT to start the next round of timing. 

Link address of the WATCHDOG TIMER driver (1) for s3c6410 under Linux