Eclipse development and debugging of ARM bare metal programs (Part 7) LCD-EEWORLD

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I originally thought that this LCD should be difficult to make, but I made it in an hour, and spent 2 hours to organize it to make my code look better. This time I can't use the simplest code to implement it like I2C. Displaying a picture requires a large image, and 4k sdram is not enough, so I have to use SDRAM. The nand, sdram, clock, and waterc_dog used for startup are all previous modules. Basically, they can be used directly, and it is not too difficult. In order to make the code have the characteristics of debugging and running at the same time. I remembered the solution of u-boot to this problem and followed it, and the effect is not bad. The principle is very simple, just make a judgment before copy_to_ram_from_nand. If the running address of _start is the link address, it means it is in debugging, so no copying is performed; if not, copying is performed. The specific code is as follows:

relocate: /* relocate U-Boot to RAM */

adrr0, _start /* r0 <- current position of code */

ldrr1, =TEXT_BASE /* test if we run from flash or RAM */

cmpr0, r1 /* don't reloc during debug */

beq stack_setup

ldr sp, =1024*4 @ Set up the stack

bl copy_to_ram_from_nand @ to SDRAM

The comments are not changed, but it is really easy to use. The complete startup code is as follows:

@File:start.S

@ Function: Set up SDRAM, transfer program to SDRAM, and then jump to SDRAM to continue execution

.equ MEM_CTL_BASE, 0x48000000

.equ TEXT_BASE, 0x33F80000

.text

.global _start

_start:

bl pre_lowlevel_init @ Turn off WATCHDOG and shield interrupts

bl system_clock_init

bl mem_ctrl_asm_init @ Set up the memory controller

bl nand_asm_init

relocate: /* relocate U-Boot to RAM */

adr r0, _start /* r0 <- current position of code */

ldr r1, =TEXT_BASE /* test if we run from flash or RAM */

cmp r0, r1 /* don't reloc during debug */

beq stack_setup

ldr sp, =1024*4 @ Set up the stack

bl copy_to_ram_from_nand @ to SDRAM

stack_setup:

ldr sp, =0x33F80000 @ Set up the stack

ldr pc, _start_armboot @ Jump to SDRAM and continue execution

_start_armboot: .word main

@stack_setup:

@ ldr sp, =1024*4 @ Set up the stack

@bl main

halt_loop:

b halt_loop

* Board-level initialization preprocessing function

* Turn off watchdog and shield interrupt

pre_lowlevel_init:

/* turn off the watchdog */

#define pWTCON 0x53000000

#define INTMSK 0x4A000008/* Interrupt-Controller base addresses */

#define INTSUBMSK 0x4A00001C

#define CLKDIVN 0x4C000014/* clock divisor register */

ldr r0, =pWTCON

mov r1, #0x0

str r1, [r0]

* mask all IRQs by setting all bits in the INTMR - default

mov r1, #0xffffffff

ldr r0, =INTMSK

str r1, [r0]

ldr r1, =0x7fff

ldr r0, =INTSUBMSK

str r1, [r0]

mov pc, lr

/* end_of pre_lowlevel_init */

* System clock initialization function

* S3C2440: FCLK:HCLK:PCLK = 1:4:8(FCLK is 405 MHz)

#define CLKDIVN 0x4C000014

#define CLK_CTL_BASE 0x4C000000

#define MDIV_405 0x7f << 12

#define PSDIV_405 0x21

#define MDIV MDIV_405

#define PSDIV PSDIV_405

#define CLKDIV 0x5 /* FCLK:HCLK:PCLK = 1:4:8 */

system_clock_init:

ldr r0, =CLKDIVN

mov r1, #CLKDIV

str r1, [r0]

* Set arm920t to asynchronous clock mode

* When reset, arm920t is in fast bus clock mode.

* Both core and AMBA are controlled by BCLK. After setting to asynchronous mode, core

* Controlled by FCLK

mrc p15, 0, r1, c1, c0, 0

orr r1, r1, #0xc0000000

mcr p15, 0, r1, c1, c0, 0

mov r1, #CLK_CTL_BASE

mov r2, #MDIV

add r2, r2, #PSDIV

str r2, [r1, #0x04] /* MPLLCON */

mov pc, lr

/* end_of system_clock_init*/

* NAND FLASH initialization function

* TACLS:TWRPH0:TWRPH1 = 1:2:1, BUS_WIDTH_8

#define S3C2440_NAND_BASE 0x4E000000

#define NFCONF_OFFSET 0x0

#define NFCONT_OFFSET 0x4

nand_asm_init:

ldr r0, =S3C2440_NAND_BASE

ldr r1, =0x001210

str r1, [r0, #NFCONF_OFFSET]

mov r1, #0x3

str r1, [r0, #NFCONT_OFFSET]

mov pc, lr

/*end_of nand_asm_init*/

mem_ctrl_asm_init:

@ Set up the memory controller to use peripherals such as SDRAM

mov r1, #MEM_CTL_BASE @ The starting address of the 13 registers of the storage controller

adrl r2, mem_cfg_val @ The starting storage address of these 13 values

add r3, r1, #52 @ 13*4 = 54

ldr r4, [r2], #4 @ Read the setting value and add 4 to r2

str r4, [r1], #4 @ Write this value to the register and add 4 to r1

cmp r1, r3 @ Determine whether all 13 registers have been set

bne 1b @ If not written, continue

mov pc, lr @ return

.align 4

mem_cfg_val:

@ Storage controller 13 register settings

.long 0x22011110 @ BWSCON

.long 0x00000700 @BANKCON0

.long 0x00000700@BANKCON1

.long 0x00000700 @BANKCON2

.long 0x00000700 @BANKCON3

.long 0x00000700 @BANKCON4

.long 0x00000700 @BANKCON5

.long 0x00018005@BANKCON6

.long 0x00018005@BANKCON7

.long 0x008C07A3 @ REFRESH

.long 0x000000B1@BANKSIZE

.long 0x00000030 @ MRSRB6

.long 0x00000030 @ MRSRB7

After starting up, it will jump to main. I won't say much about the LCD parameters. I have used RVDS before and there is no problem. Many blogs and textbooks explain it very clearly. Here I will mainly write about the implementation process.

Debug screenshots:

Eclipse development and debugging of ARM bare metal programs (Part 7) LCD

Display screenshot:

Code: http://download.csdn.net/detail/kangear/5268137

Keywords：Eclipse Reference address：Eclipse development and debugging of ARM bare metal programs (Part 7) LCD

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Next article：Developing and debugging ARM bare metal programs in Eclipse (V) MMU debugging

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