ARM Cortex-M3 Study Notes (4-1)

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I'm studying ARM Cortex-M3 recently, and I found a book called "An Definitive Guide to The ARM Cortex-M3" which is considered a classic. This series of study notes is actually the reading notes I made while studying this book.

 

Chapter 4 Instruction System

Basic syntax

The assembly syntax introduced here is the syntax of the ARM assembler. If other assemblers are used, such as as in gcc, the syntax is different.

 

A typical pattern of assembly instructions is as follows:

Label

opcode operand1, operand2, … ;comment

 

The label is optional. If there is one, it must be written at the top of the page and there is no need for a ":" after the label.

The opcode is the mnemonic for the instruction and must be preceded by at least one space character.

 

The immediate value must start with "#", and the hexadecimal number representation method is the same as that of C language, for example:

MOV R0, #0x12 ; R0  0x12

 

Use the EQU directive to define constants:

 

NVIC_IRQ_SETEN0 EQU 0xE000E100 ; Note: constant definitions must be written at the top of the line

NVIC_IRQ0_ENABLE EQU 0x1

LDR R0, =NVIC_IRQ_SETEN0; Here LDR is a pseudo instruction, which will be converted by the assembler

; A "PC-relative load instruction"

MOV R1, #NVIC_IRQ0_ENABLE ; transfer the immediate value to R1

 

DCI can insert 1 half word (2 bytes) into the assembly code. This instruction is usually used to insert instructions that the assembler does not support.

DCB defines a string of byte constants

DCD defines a string of 32-bit integers

For example, the following example:

LDR R3, =MY_NUMBER ; R3= MY_NUMBER

LDR R4, [R3] ; R4= *R3

LDR R0, =HELLO_TEXT; R0= HELLO_TEXT

BL PrintText ; Call PrintText to display the string, R0 passes the parameter

MY_NUMBER

DCD 0x12345678

HELLO_TEXT

DCB "Hello\n",0

 

 

Instruction suffix

suffix

meaning

S

Request to update the relevant flags in APSR, for example:

ADDS R0, R1 ; Update the flag in APSR according to the result of addition

EQ,NE,LT,GT, etc.

Conditionally execute instructions.

EQ=Euqal, NE= Not Equal, LT= Less Than, GT= Greater Than, for example:

BEQ

 

Unified Assembly Language (UAL)

Along with the Thumb-2 instruction set, a new assembly syntax (unified assembly language) also appeared. Using the syntax of the unified assembly language, we can easily choose whether the current statement is compiled into a 16-bit instruction or a 32-bit instruction.

ADD R0, R1 ; Use traditional Thumb syntax

ADD R0, R0, R1 ; Equivalent writing allowed after the introduction of UAL (R0=R0+R1)

 

If you use traditional Thumb syntax, some instructions will update the APSR by default.

If you use the UAL syntax, you must specify the S suffix to update. For example:

AND R0, R1 ; Traditional Thumb syntax

ANDS R0, R0, R1 ; equivalent UAL syntax (must have S suffix)

 

The .W (Wide) suffix specifies 32-bit instructions, and the .N suffix specifies 16-bit instructions. If no suffix is ​​given, the assembler will first try to use 16-bit instructions to slim down the code, and if that doesn't work, it will use 32-bit instructions. For example:

ADDS R0, #1 ; The assembler will use 16-bit instructions to save space

ADDS.N R0, #1 ;Specify the use of 16-bit instructions (N = Narrow)

ADDS.W R0, #1 ;Specify the use of 32-bit instructions (W=Wide)

 

32-bit Thumb-2 instructions can be half-word aligned. Not having word alignment makes it easy to mix 16-bit instructions and 32-bit instructions in the code.

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Keywords:ARM  Cortex-M3 Reference address:ARM Cortex-M3 Study Notes (4-1)

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