Data Acquisition System Based on RS-485 Bus

　　1.1 System overall block diagram

　　The system is essentially a distributed control system, or more precisely a remote data acquisition system. The system conceptual design diagram is shown in Figure 1, and the system overall framework diagram is shown in Figure 2.

　　1.2 System Module Design

　　1.2.1 Signal acquisition module

　　The system collects deformations at all positions in the dam, which reflects the pressure values ​​at all positions. The NZS-25 series differential resistance strain gauge is selected. It is a large-range strain gauge suitable for measuring strains inside dams and other concrete buildings, steel structures, etc. It is different from the structure of general pressure sensors in that it obtains pressure values ​​by measuring ratios. Its basic structure is shown in Figure 3.

　　In Figure 3, R1 and R2 are sensitive resistors with a base resistance of 40Ω. When they are not under pressure, the resistance of the two resistors will not change. However, when under external pressure, the resistance of R1 will change with the pressure and remain unchanged. In this way, the voltage drops on R1 and R2 are different. The voltage drops on R1 and R2 are obtained through two measurements, and their ratio is calculated through the program to reflect the change in pressure.

　　1.2.2 Signal Amplification Module

　　The pressure sensor used in the system outputs a voltage signal at the mV level. The voltage signal is too small to be directly converted to A/D, so it must be amplified to meet the requirements of the converter. A dedicated instrument amplifier AD620 chip is selected. This chip uses differential input internally, with a high common-mode rejection ratio, large differential input impedance, high gain, very good accuracy, and a simple external interface. The analog input voltage provided by the AD620 amplifier to the A/D converter is -2 to 2V, which meets the requirements of the A/D converter.

　　1.2.3 A/D conversion module

　　The conversion module uses the ICL7135 chip, and its typical configuration is shown in Figure 4.

　　The clock of ICL7135 is provided by the ALE terminal of the lower microcontroller. Since the lower microcontroller does not have an extended peripheral program memory and data memory at the P0 and P2 ports, the clock frequency provided by the terminal is 1/12 of the system clock frequency. In addition, since the preamplifier uses AD620, which is dual-powered, ICL7135 is also dual-powered, and their power requirements are the same. The connection between ICL7135 and the lower microcontroller adopts a serial connection, as shown in Figure 5.

　　1.2.4 Power Module

　　Since the system's lower computer is located at the dam site, power cannot be obtained from the site and must be provided by the upper computer. Therefore, the power supply solution is shown in Figure 6.

　　In the main node part, the AC 220V is converted into DC 12V through the main power processing module. The power supply of the upper computer is provided by its own 5V voltage regulator module, and the 12V DC is transmitted to the lower computer through the main power line. The power required by the lower computer and its peripheral devices is provided by the power module of the lower computer. The special voltage required by individual devices is obtained by a dedicated module.

　　1.2.5 Communication Module

　　The bus adopts twisted pair differential transmission mode, which can be connected in half-duplex and full-duplex mode, with a maximum transmission distance of 112km. The system data communication adopts half-duplex communication mode, that is, only one node in the entire network can be the master node at any time, in the sending state, and send data to the bus, and the other nodes must be in the receiving state. If two or more nodes send data to the bus at the same time, all senders will fail to send data. Therefore, the communication network generally adopts the master-slave mode, that is, the master node controls the communication timing of the entire network, so that each node on the bus uses the bus in a time-sharing manner to resolve the conflict of bus data transmission.

　　The bus driver chip uses the RS-485 interface chip SN75LBC184, which uses a single power supply and can work normally when the voltage is 3~515V. Compared with ordinary chips, it can not only resist the impact of lightning, but also withstand the electrostatic discharge impact of up to 1000V. The chip integrates 4 instantaneous overvoltage protection tubes, which can withstand the transient pulse voltage of up to 1000V, so it can significantly improve the reliability of preventing lightning damage to the device. For some sites with relatively harsh environments, it can be directly connected to the transmission line without any external protection components. The chip also has a unique design. When the input end is open, its output is high level, which can ensure that the normal operation of the system is not affected when there is an open circuit fault in the cable at the input end of the receiver. In addition, its input impedance is twice the standard input impedance of RS-485 (≥24kΩ), so 64 transceivers can be connected to the bus. The chip is designed with a limited slope drive so that the output signal edge will not be too steep and too many high-frequency components will not be generated on the transmission line, thereby effectively suppressing electromagnetic interference. The connection between the bus driver chip and the microcontroller is an indirect connection, as shown in Figure 7.

　　

　　1.2.6 Data Storage Module

　　This module is used to store the pressure data transmitted from the lower computer. The basic requirements of the system for the data storage device are large storage capacity, data that is not easily lost when power is off, can be saved for a long time, and easy to expand capacity. Based on the above requirements, 24C256 that follows the bus serial expansion technology is selected. The data exchange between the microcontroller and 24C256 fully complies with the provisions of the IIC bus, that is, the microcontroller is the host and the 24C256 is the slave. All operations are determined by the status of the SDA and SCL pins (a total of 4 states: start, stop, data and response). The connection diagram of 24C256 and the microcontroller is shown in Figure 8.

　　1.2.7 Clock module

　　The real-time clock chip DS12C887 is used to generate the time base for the system. Its connection with the microcontroller is shown in Figure 9. It can be treated as the external RAM of the microcontroller. The DS12C887 is operated through the P0 port, and an interrupt is sent to the microcontroller through its interrupt pin IRQ, so that the microcontroller can read the time.

　　2 Software Design

　　The system software block diagram is shown in Figure 10. The first-level directory is divided into upper computer program, communication program and lower computer program; the second-level directory is divided into data acquisition program module, analog multi-way switch control program module, data processing program module, lower computer communication program module, upper computer communication program module, display program module, storage program module, clock program module and keyboard control module. Each second-level program module is composed of smaller functions, and this design method is easy to modify and test.

　　3 Conclusion

　　The software program is designed according to the top-down principle. The functions of each module are implemented by C language programming according to the functional modularization. The modules are encapsulated in the form of subroutines to provide the specified interface to the outside world. The modules are then combined according to the system flow requirements to finally realize the entire system.