ARM processor mode switching (including MRS, MSR instructions)

1.1.1 ARM processor mode switching (including MRS, MSR instructions)

Except for user mode and system mode, all other modes have a private SPSR status register to save the execution status before switching to the mode. The reason why user mode and system mode do not have SPSR is that the CPU usually executes in user mode most of the time. When an exception or system call occurs, it will switch to other modes to save the status in user mode. When switching back to the original mode, it can directly restore the value of SPSR to CPSR. Therefore, SPSR is not required in user mode and system mode. For detailed operations, see the exception handling in the next section.
The above modes are distinguished by the M[4:0] bit in CPSR, as shown in Figure 3-1:


Figure 3-1 CPSR control bit
Switch to different modes by writing corresponding data to the mode bit M[4:0]. When operating the CPSR and SPSR registers, general instructions such as mov and ldr cannot be used. Only privileged instructions msr and mrs can be used.
In ARM processors, only the MRS (Move to Register from State register) instruction can read the status registers CPSR and SPSR. The current working status of the processor can be obtained by reading CPSR. Reading the SPSR register can obtain the processor status before entering the exception (because the SPSR register is only available in exception mode).
For example:
The MRS instruction can be used to obtain the value in the status register, and then compare the value of its mode bit M[4:0] to determine the current mode. Of course, other corresponding bits can also be compared to understand the current CPU status.
Similarly, in ARM processors, only the MSR instruction can write to the status registers CPSR and SPSR. Used in conjunction with MRS, read-modify-write operations on the CPSR or SPSR registers can be implemented, the processor mode can be switched, or IRQ/FIQ interrupts can be enabled/disabled, etc.
Since the xPSR register represents the status of the CPU, each bit has a special meaning. When writing to the xPSR status register (this usage does not exist when reading), in order to prevent misoperation and facilitate memory, the 32 bits in the xPSR are divided into four areas, each represented by a lowercase letter:
When writing to the corresponding area, use xPSR_x to specify the write area without affecting other bits of the status register, such as
enabling IRQ interrupt:
Disable IRQ interrupts:
The following table lists the binary representation of different modes:
Table 3-3 Binary representation of different working modes

Mode Name	user	Fast interruption	Interrupt	manage	Suspension	Undefined	system
M[4:0]	10000	10001	10010	10011	10111	11011	11111

When initializing the development board, specify the stack space for different modes. The following example initializes the stack pointer sp of each mode:
stack_init; Stack pointer initialization function
    @ undefine_stack                                       
    msr cpsr_c, #0xdb; Switch to undefined exception
    ldr sp, =0x34000000; The stack pointer is the highest memory address, and the stack is a reverse stack
                                                                            ; The last 1M of the stack space 0x34000000~0x33f00000
    @ abort_stack                                                      
    msr cpsr_c, #0xd7; Switch to termination exception mode
    ldr sp, =0x33f00000; The stack space is 1M, 0x33f00000~0x33e00000
    @ irq_stack                                                
    msr cpsr_c, #0xd2; Switch to interrupt mode
    ldr sp, =0x33e00000 ; The stack space is 1M, 0x33e00000~0x33d00000
    @ sys_stack                                               
    msr cpsr_c, #0xdf ; Switch to system mode
    ldr sp, =0x33d00000 ; The stack space is 1M, 0x33d00000~0x33c00000
    msr cpsr_c, #0xd3 ; Switch back to management mode
    mov pc, lr