How to write ISE constraint file *.ucf

I have never understood why the AC97 IP downloaded from the official website cannot run. The whole IP is just an empty shell. When bit_clk is input, no signal is output. From the RTL of the IP, even if the IP is not connected to the CPU BUS, as long as it is integrated into the FPGA, when the BIT_CLK signal is input to the IP, SD_OUT and SYNC should have data and signal outputs. But the strange thing is that they are either high or low, and they don't jump at all. Obviously, the output signal of the IP is not successfully output to the pin.

Later I found out that it was a constraint problem. It seems that constraints are really important for FPGA design.

The following are several commonly used constraint statements for your reference. 

NET "clk0"  TNM_NET = "sys_clk_grp";  #Add a TNM_NET constraint to the clock network clk, and define all synchronous elements driven by clk0 as a group named sys_clk 

#Use TIMESPEC to constrain the period of sys_clk_grp

TIMESPEC "TS_ sys_clk_grp " = PERIOD " sys_clk_grp " 9.9 ns HIGH 50 %; #The period is 9.9ns. HIGH indicates that the first pulse in the clock cycle is a high level. If it is LOW, it means a low level, and the duty cycle is 50% 

# FROM_TO is used to define the timing constraints between two logical groups

#语法：TIMESPEC "TS_name " = FROM "group1" TO " group2" value;

TIMESPEC "TS_p2s" = FROM "pads" TO "ffs" 10;  # pads到ffs延迟10ns 

#Maximum skew constraint MAXSKEW is used to describe the time difference between the clock signal driven by the same point and reaching two or more end points after propagating through the path

NET “AC97_Bit_Clk” MAXSKEW =10ns;

 NET  tft_wr LOC=C11  |  ISTANDARD = LVCMOS33;

NET clk0 IOSTANDARD = LVCMOS33; #IO level standards include LVCMOS25, LVTTL, SSTL2_I, LVDCI_33, etc.  

NET sys_rst_in LOC = D6;

NET sys_rst_in PULLUP; #PULLUP, PULLDOWN pull-up and pull-down settings

NET sys_rst_in TIG;# TIG (Timing Ignore) does not perform timing constraints

 NET SYNC     DRIVE = 8 | SLEW = SLOW; # DRIVE: minimum drive current, unit mA, can have 2, 4, 6, 8, 12, 16 modes, SLEW = {FAST|SLOW|QUIETIO}, QUIETIO is only used in Spartan-3A. SLEW is slew, if slew=fast, overshoot will occur, at this time, if DRIVE is very large (12mA), it will cause severe distortion of output power, which may not meet the requirements of external devices. 

#Wildcards

NET gpio_char_lcd<6> LOC = AE13;

NET gpio_char_lcd<5> LOC = AC17;

NET gpio_char_lcd<4> LOC = AB17;

NET gpio_char_lcd<3> LOC = AF12;

NET gpio_char_lcd<2> LOC = AE12;

NET gpio_char_lcd<1> LOC = AC10;

NET gpio_char_lcd<0> LOC = AB10;

NET gpio_char_lcd<*> ISTANDARD = LVCMOS33;

NET gpio_char_lcd<*> TIG;

NET gpio_char_lcd<*> PULLDOWN;   # * represents any string

 #Region constraints

# Locate DCM/BUFG - Tools can probably figure them out automatically

#                   but just LOC them down to be safe

INST dcm_0/dcm_0/DCM_ADV_INST LOC = DCM_ADV_X0Y1;

INST dcm_1/dcm_1/DCM_ADV_INST LOC = DCM_ADV_X0Y2;

INST dcm_2/dcm_2/DCM_ADV_INST LOC = DCM_ADV_X0Y0; 

INST dcm_0/dcm_0/CLK0_BUFG_INST  LOC = BUFGCTRL_X0Y0;

INST dcm_0/dcm_0/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y1;

INST dcm_0/dcm_0/CLKDV_BUFG_INST LOC = BUFGCTRL_X0Y2; 

INST dcm_1/dcm_1/CLK0_BUFG_INST  LOC = BUFGCTRL_X0Y31;

INST dcm_1/dcm_1/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y30;

 The constraints of the area are equivalent to specifying the location of a specific type of device during the layout process. This can be set entirely through the GUI interface of FloorPlanner. After setting it up with the graphical interface, the configuration information will be placed in UCF. Here we only introduce the use of UCF.

For example:

INST  "Done"  LOC  = "SLICE_X32Y163" ;    #Done is mapped to a register, mapped to the position of SLICE_X32Y163. (32, 163) is equivalent to a coordinate, which can be viewed with FloorPlanner. INST "BRAM4/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v4_init.ram/TRUE_DP.SINGLE_PRIM.TDP" LOC  = "RAMB16_X2Y22" ; #A mapping of RAM16.

For example, X, Y, and Z correspond to registers. Now if I want to put them in a specified area, I can write it like this:

INST “X” AREA_GROUP = reg;

INST “X” AREA_GROUP = reg;

INST “X” AREA_GROUP = reg;

AREA_GROUP reg RANGE = SLICE_X1Y1 :SLICE_X1Y6;