I2C bus serial input and output structure-EEWORLD

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This article takes the IIC bus serial input and output structure of 8XC552 (a microcontroller from Philips) as an example to deeply understand the IIC bus protocol:

The serial input and output structure of the IIC bus ensures that the data register of the IIC bus can store the latest data on the bus. SDAT and ACK form a 9-bit shift register, which forms a ring structure. The data on the bus is continuously sampled while the serial output is in progress. The ACK flag is controlled by the bus and can be accessed by the CPU (1 is stored for non-acknowledgement, and 0 is stored for acknowledgement). On the rising edge of the clock pulse on the SCL line, the serial data is stored in SDAT through the ACK flag, and the serial data is shifted out along BSD7 on the falling edge of the SCL clock pulse. When a byte of data is shifted into SADT, the data in SDAT is valid, and the control logic sends the acknowledgement bit in the 9th clock pulse cycle.

Why must the data on the data line remain stable when the clock signal is high when the IIC bus is sending data? This is because the data on the bus will be collected during the high level period. If the data on the bus is unstable at this time, the collected data and the sent data will be inconsistent, thus shutting down the transmission (similar to arbitration failure). The protocol stipulates that the high or low level of the data line is allowed to change only when the clock signal is low. This is because the data in BSD7 is sent on the falling edge of the clock, and the data on the bus will not be collected during the low level of the clock pulse.

When the CPU writes to SDAT, SDAT7 is loaded with BSD7, which is the first bit of data sent to the SDA line. After 9 clock pulses, the 8-bit data in SADT is sent to the SAD line, and the acknowledgement bit appears in ACK. In this way, the data sent to the bus is returned to SDAT.

The SDA register contains the data to be sent or a data byte just received. When sending, the data is always shifted from right to left. When the data is shifted out, the data on the bus is shifted in at the same time. This structure of the shift register ensures that the data will not be lost when the bus competition fails. It is connected to the internal bus in parallel and to SDA in serial. When sending data, it is loaded into SDAT by the internal bus. When sending, the data is returned to SDAT in serial from the serial channel. When receiving, the newly received data on the SDA line is loaded.

Reference address：I2C bus serial input and output structure

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