STM32F107VC PLL initialization

AHB：advanced high-performance bus；APB： advanced peripherals bus。

static void SetSysClockTo72(void)
{
  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  
  /*

     SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------

      SYSCLK is obtained by PLL clock, external high-speed clock, internal high-speed clock, and the maximum is 72MHz

      HCLK is obtained by HCLK through AHB pre-divider, up to 72MHz, to AHB bus, core memory and DMA

      PCLK2 maximum 72MHz, to APB2 peripherals

      PCLK1 maximum 36MHz, to APB1 peripheral

*/    
  /* Enable high-speed external crystal oscillator*/    
  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
 
  /* Wait for external high-speed clock to stabilize*/
  do
  {
    HSEStatus = RCC->CR & RCC_CR_HSERDY;
    StartUpCounter++;  
  } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));

  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
  {
    HSEStatus = (uint32_t)0x01;
  }
  else
  {
    HSEStatus = (uint32_t)0x00;
  } 

  if (HSEStatus == (uint32_t)0x01)
  {
    /* FLASH access control register configuration enable prefetch, two wait cycles (36MHz --72MHz is 2 wait cycles) */
    FLASH->ACR |= FLASH_ACR_PRFTBE;

    /* Flash 2 wait state */
    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;   

    /* Initialize HCLK PCLK1 PCLK2 first

       The clock configuration register should be initialized to 0 at power-on. The result of the following configuration is:

       8M high-speed internal clock is the system clock

       HCLK = 8M

       PCLK2 = 8M

       PCLK1 = 4M

 */
    /* HCLK = SYSCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
      
    /* PCLK2 = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
    
    /* PCLK1 = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;

#ifdef STM32F10X_CL
    /* Configure PLLs ------------------------------------------------------*/

    /* If STM32F10x_CL is defined, configure as follows. This macro definition is defined in the compilation options*/
    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
    /*

        PLL2 configuration: Clock signal input source is PREDIV1, 8 times frequency and then divided by 5 
   */

    /*Clear related control fields*/      

  RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);

   /* 配置CFGR2寄存器*/
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
  
    /* Enable PLL2 */
    RCC->CR |= RCC_CR_PLL2ON;
    /* Wait till PLL2 is ready */
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
    {
    }
    
   
    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
                            RCC_CFGR_PLLMULL9); 
#else    
    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
                                        RCC_CFGR_PLLMULL));
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
#endif /* STM32F10X_CL */

   /* Enable PLL   使能PLL */
    RCC->CR |= RCC_CR_PLLON;

    /* Wait till PLL is ready */
    while((RCC->CR & RCC_CR_PLLRDY) == 0)
    {
    }
    
    /*

      Select PLL as system clock source

       Select the PLL clock as the system clock and wait for it to stabilize 

 */ 
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;   

    /* Wait till PLL is used as system clock source */
    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
    {
    }
  }
  else
  { /* If HSE fails to start-up, the application will have wrong clock 
         configuration. User can add here some code to deal with this error */
  }
}

HSE (25MHZ) -> PREDIV2 (5-frequency division) - 5MHZ - > PLL2MUL (8-frequency multiplication) - 40MHZ - > PREDIV1SCR (PLL2 selection) - 40MHZ - > PREDIV1 (5-frequency division) - 8MHZ - > PLLSCR (PREDIV1 input) - 8MHZ - > PLLMUL (9-frequency multiplication) - 72MHZ - > SW (PLL selection) - SYSCLK (72MHZ).